

                          An Overview of the
                     Advanced Amiga Architecture
                     and Other Future Directions


                       Document Revision 1.0

                1993 Developers Conference Release


                           by Dave Haynie
                    Advanced Amiga Systems Group


- 4*Chips VSLI, high speed CMOS
- AAA chip set was gleaned, adapted from AGA chip set
- AAA is largely compatible with ECS
- AA registers are not supported in AAA
- ECS compatibility is to be eliminated
- CPU bus can master the entire chip bus for more efficient CPU to
  CHIP bus access


MEMORY BAND WITH
================

- AAA chips run a 4 cycle burst to Chip RAM, i.e. 4.56 * ECS or 1.14 times
  AGA`s two-cycle burst
- Bursts of up to 512 words can be run to keep up with hi-res displays.


CPU BAND WITH
=============

- CPU access to Chip RAM is improved
- AAA chips manage an asynchronous interface to the CPU.
- CPU with some extra support logic can completly master the AAA chip
  RAM bus, allowing Chip RAM access as fast as today`s 32-bit Fast RAM.


CPU BUS DMA
===========

- AAA chip bus DMA activity is dynamically managed.
- 40 DMA channels, with dynamic allocation between BLITTER <-> CPU


BLITTER
=======

- AAA blitter is much faster than today`s
- It scrolls 640*200*2 6 times the speed, 640*200*4 9 times faster than the
  pld Blitter
- It has a 32-bitmode which operates in pixel addressing and can handle the
  chunky modes aswell (2,4,8,16 bits)
- Line draw has auto clipping.
- Blitter has arithmetic function now like "sort" and "tally" at any pixel
  depth, addition, average, subtracing, saturated subtractions, etc.

Blitter speeds:

DRAM single
       2 planes @ 640*200 =  489.06 frames/sec
      16 planes @ 640*200 =   41.61 frames/sec
       2 planes @ 800*560 =  124.54 frames/sec
       8 planes @ 800*560 =   14.96 frames/sec

VRAM single
       2 planes @ 640*200 = 504.23 frames/sec
      16 planes @ 640*200 =  56.78 frames/sec
       2 planes @ 800*560 = 124.54 frames/sec
       8 planes @ 800*560 =  14.96 frames/sec


COPPER
======

- Copper handles 32-bit operations
- Supports move-multiple
- Copper has interrupt capability, let it receive ints from blitter


GRAPHICS
========

single chipset system  (A1400 ?? Ed.)
       DRAM system:
            800*560*9 planes
       VRAM system:
            800*560*13 planes or 800*560*24 using "hybrid pixels"

dual chipset system   (A5000 ?? Ed.)
       DRAM system:
            1280*1024*5 planes
       VRAM system:
            1280*1024*8 planes or 1024*768*24 using "hybrid pixels"
(--> ADIOS PC!!! Ed.)

- sprites are now 128 pixels wide.
- 16 planes supported, 8-bit playfields
- AAA pixel clock is no longer ties to the AAA bus clock
- pixel clocks can be scaled

NEW MODES
         HAM10
         HALF-CHUNKY- 2,4 or 8 bit depths
         CHUNKY-      16 bits (5bit guns) no palette
         HYBRID-      24 bits, seperate chunky planes
         PACKLUT-     2 bits per pixel decompress to 8-bit half chunky,
                      in 4*4 pixel regions, each region has colors,
                      8-bit values indexed thru CLUT and 16 pixels
         PACKHY-      4 bits per pixel decompress to 24-bit direct pixels
                      in 4*4 pixel regions, each region has colors
                      24-bit direct values and sixteen pixels


VIDEO CAPTURE
=============

- AAA pixel bus is reversed, (ONLY ON VRAM), capture to any chunky mode


SOUND
=====

- 64 khz with 16-bit resolution
- 8 channels, both sides i.e. 1 channel on both sides with different volume
- 8-bit audio sampling is also supported


FLOPPY DISKS
============

- 2 or 4 megs per disks direct, no tricks to it!!!
- built in decoding hardware MFM, (RLL2,7), Biphase Mark (CD-ROM)
- xfer in track, sector and CD-MODE and a high speed track mode
- xfer rate is 20 times faster 11.4 Mbit/sec from 0.5 Mbit/sec through
  DMA peek is 9.9 Mbit/sec
- hardware can decode IBM format aswell
- MAC format supported aswell with software


UART
====

- 2 UARTS are supported, 4-byte FIFO


AAA chips descriptions
======================

1. Andrea - chip bus controller
          - chip ram control
          - "high-priority" bus request allows external device to master
            the chip ram bus rather than Andrea
          - CPU bus gating
          - manages clocking of both CHIP and Video display
            8 possible pixel clock values at any time
          - Video timing hsync, vsync etc...
          - Blitter, pixel addressing / arithmetic modes

2. Monica - new display controller
          - It takes in display timing data generated by Andrea and
            graphics data fetched by Linda and from that generates
            25-bit digital and analog RGB output (24bit color,1bit genlock)
          - HAM mode logic, sprites, color regs

3. Mary   - controls types of I/O
          DISK CONTROLLER
          - raw bit with = 88-9000ns
          - max raw bit rate = 11.4 Mbit/sec
          - hardware encoding = raw GCR MFM RLL(2,7) BiPhase Mark
          - sync = 32, 17, 8-bit
          - xfer modes = track sector cd-digital track-plus
          - hardware CRC (sector/track)
          - async PLL clock
          - input types = pulse, NRZ

          AUDIO CONTROLLER
          - sample rate = 64 khz
          - channels = 8
          - volume = 12bit signed
          - volume aliasing = no
          - sample size = 8/16 bits
          - digital output
          - dynamic range = 16 bits
          - channels left/right = 0-7 on both sides
          - global mono bit
          - period resolution = 280/64ns
          - 8-bit sampler supported using th pot-in lines

4. Linda  - double buffers full display lines
          - while one complete line of Linda`s line buffers, the next line is
            being fetched into Linda`s other line buffer
          - PACKLUT, PACKHY modes are decoded here

- Between them are, 256 word regs (ECS compatible)
- 384 longword address regs (new stuff)
- 512 longword address CLUT registers


FUTURE SYSTEM DESIGN
====================

- Processor-independent system bus optimized for chip to chip interconnect
- Motherboard will be a basic design
- CPU, Amiga, CHIPs and other various elements will be located on seperate
  modules (cards)


AMIGA DSP
=========
AT&T DSP3210
- 32-bit floating point artithmetic
- 32-bit addressing
- large 8K on-chip cache 0wait
- 33Mflops of power
- shared bus with Motorola CPU
- Serial I/O with DMA 24 Mbits/sec
- Barrel shifter
- mu-law & A-law encoding
- Bit I/O general purpose 8-bit I/O port

it can emulate:
- V32 / V22bis MNP5 / V29 G3 fax / modem emulation with fallback
- subband coder
- G.722 7khz speech coder (1000% better than SAY)
- DTMF generator/decoder
- JPEG still/ MPEG encode/decode
- Call progres detector
- Non integer sample rate converter
- delta-ceptrum feature extractor
- text to phones LPC, LPC to speach
- speech recognizer
- talker verification
- 3d GFX library
- MIDI music synth with EMU proteus soundlibs
- perceptual image coder
- perceptual audio coder

AMIGA VCOS software Architecture:

    VCD - applications
     |
     |
 (vc)     vcas.library
     |
     |
     dsp3210.device---dsp3210.resource
                    |
                    |
 (ve)                   DSPEntry-->DSPEntry-->DSPEntryN
                    |    |     |     |    |     |
                 IntProc |  IntProc  |  IntProc |
               IntServer | IntServer | IntServer|
                    |    |     |     |   |      |
                   HardWare   HardWare   HardWare

=====================================================================

Much Fun with this great new machines which will hopefully come out
in Fall 1994 at the AmiExpo in Cologne !!!

           Typed by FeNrIs / InTeRaCtIvE

