

   Author: Christopher J Burian
   Subject: LCD [technical] FAQ (first edition)
   Version: 0.00
   Date: 14 Jul 1994
   E-mail: cburian@ux4.cso.uiuc.edu
   
   Trademark and Copyright notice:
   
   Trademarks and service marks appearing in this FAQ are the property of
   their respective owners. Copyright 1994 by Christopher Burian and
   other contributors. All rights reserved. Permission is granted to
   distribute and reproduce this FAQ freely as long as this notice and
   all attributions remain intact. Please email cburian@uiuc.edu with any
   suggestions, additions, or corrections. Have a groovy day.
   
------------------------------------------------------------------------
Part 1 of 3   (Find other Parts by search for this flag "Part x of 3") 

 
                         CONTENTS: Part 1
                                       
0.0 LCD FAQ introduction
      Why this FAQ?
      Author
      General description of LCDs
      References
      Where to find this FAQ
      Definitions
1.0 Sources for modules
2.0 Specs
 2.1  Pin description
 2.2  Character set
 2.3  Instruction set
 2.4  Timing
 2.5  Memory map
  2.5.1  Custom characters
  2.5.2  Addressing display ram
 2.6  Initialization
  2.6.1  Initialize for 8-bit operation
  2.6.2  Initialize for 4-bit operation
3.0  Interfacing
 3.1  Manual test circuit
 3.2  Interfacing to CPU bus
 3.3  Interfacing to CPU port
 3.4  Interfacing to Parallax BASIC STAMP
 3.5  Serial Interface

   
     _________________________________________________________________
   
   0.0 LCD FAQ introduction
   
   I'm writing now what I wish I had about four months ago, when I first
   started playing with LCD character display modules. I still haven't
   figured out the graphics units yet, so no info on those is included.
   This FAQ is geared towards hobbyists and experimenters. I think it'll
   help anyone who finds the datasheets somewhat terse.
   
   Any errors are all mine. Please email suggestions, additions or
   corrections to Chris Burian at <cburian@uiuc.edu>
   
   LCDs are manufactured by quite a few different companies. Units
   typically seen in the surplus market come from Densitron, Epson,
   Hewlett Packard, Optrex, or Sharp. Common configurations are 16, 20,
   24, 32, or 40 characters by 1, 2, or 4 lines.
   
   I've been loose with the term LCD here. One can find LCDs at any level
   of integration from what looks like a glass slide and will need
   drivers and controller, to a module that includes the row and column
   drivers, to the modules I'm actually talking about which also include
   the controller (usually a Hitachi HD44780). I'd recommend staying away
   from modules that do not say they have a controller or otherwise
   indicate that it's included, such as by describing the character set
   or noting an ASCII interface. The units to look for are usually called
   character-type dot matrix LCD modules.
   
   Most of the modules I've seen use the Hitachi controller, such as the
   Densitron, Optrex, and Sharp models. These all use the same interface,
   and have the same character set and memory map. This FAQ right now is
   only good for LCD's with Hitachi controllers. Later, this FAQ will
   hopefully include data on modules that use SMOS brand controllers,
   like Seiko and Epson modules.
   
   References used to generate [FAQ] version 0.00:
   
     * OPTREX Dot Matrix LCD Module datasheet
     * June '94 issue of Nuts & Volts magazine
     * Intel Embedded Control Applications book-1988
     * Texas Instruments TTL Logic Data Book-1988
     * The Miniboard 2.0 Technical Reference by Fred G. Martin,
     * Mobile Robots: Inspiration to Implementation by Joseph Jones and
       Anita Flynn
       
   The current version will be available on the ftp site
   bode.ee.ualberta.ca, somewhere in /pub/cookbook, and will be
   occasionally posted to comp.robotics and sci.electronics.
   
   Some definitions:
   
     * LCD: Liquid Crystal Display
     * Supertwist: a design that improves contrast
     * Backlit: uses lamp behind the display instead of reflected light
     * Electroluminescent: a kind of lamp that gives off a cool glow,
       powered by hi-voltage AC, typically powered with a converter
     * LED: Light Emitting Diode, the other popular backlight
     * Extended temperature: modules designed for (surprise) use in
       temperatures outside the standard range. Standard range is 0 to 50
       C, extended range is -20 to 70 C. Extended range units need -7VDC
       as well as +5VDC. Standard range units need only +5VDC.
     * Driver: LCD modules of all sorts have column and row, or x and y,
       drivers. To control one of these modules directly from a CPU would
       take a great deal of time and software overhead, because each bit
       (dot) has to be written separately, usually 4 dots at a time.
     * Controller: the chip, such as an HD44780 or SED1130, which acts as
       an interface between your CPU and the row and column drivers. It
       may have on-chip ram, or may need external ram. The controller
       takes care of generating characters, refreshing the display, and
       so on. The modules discussed in this FAQ have integral
       controllers.
       
   1.0 sources for modules
   
   These are the sourses I've seen that are most accessible to the
   hobbyist. If you know of more, please email me.
   

Company                   Telephone

All Electronics           1-818-904-0524
B. G. Micro               1-214-271-5546
Cronin Electronics        1-617-449-5000
Digikey Corporation       1-800-DIG-IKEY
Herbach & Rademan         1-215-788-5583
Hosfelt Electronics       1-800-524-6464

...and hundreds more, no doubt.

   My favorite references are the Optrex databook for dot matrix modules,
   available from Digikey for $2, and the Amateur Robotics column in the
   June '94 issue of Nuts & Volts magazine, 430 Princeland Court, Corona,
   CA 91719.
   
   2.0 specs
   
   2.1 Pin description
   
   These numbers are the same no matter the physical arrangement of the
   pins, (for instance, a row along the top on Optrex units, or a 2x7
   .100" center array on the side of Sharp units).
   

Pin#  Symbol  Level  Function
====  ======  =====  =======================================
 1     Vss     GND    Ground
 2     Vcc     +5V    Module power
 3     Vee    Note1   Liquid crystal drive
 4     RS      H/L    Register select, H=data, L=instruction
 5     R/W     H/L    Read/Write, H=read (module->CPU),
                      L=write (CPU->module)
 6     E       H/L    Enable
 7     DB0    Note2   Data bit 0  (least significant bit)
 8     DB1      "
 9     DB2      "
10     DB3      "
11     DB4      "
12     DB5      "
13     DB6      "
14     DB7      "

   Backlight drive: If the module has a back light, it will be driven by
   a pair of pads separate from the interface pads. Check your datasheet
   for power requirements. Electroluminescent strips usually need 100VAC
   from a DC-AC converter driven off the 5V power supply.
   
   Note1: On standard modules Vee is between GND and 5V, on temperature
   extended modules it is between GND and -7V. The potentiometer is the
   contrast adjustment.
   
   Standard:
   

+5V ------------*----------- Vcc
                |
                /
        10k to  \<---------- Vee
        20k pot /
                \
                |
GND ------------*----------- Vss

   
   
   Temperature extended model:
   

+5V ------------------------ Vcc

GND ------------*----------- Vss
                |
                /
        10k to  \<---------- Vee
        20k pot /
                \
                |
-7V ------------'

   
   
   Extended temperature types may also employ fancy temperature
   correction circuitry to provide automatic contrast adjustment.
   
   Note2: For an 8-bit interface, DB7-DB0 are driven by your CPU on a
   write but must be switched to hi-Z (or pulled up with pullup resistors
   only) so the module can drive them on a read. For a 4-bit interface,
   only DB7-DB4 are used. The most significant nybble is written first
   (bit7-bit4), then the least significant nybble is written (bit3-bit0)
   on the next Enable cycle. DB3 to DB0 are left unconnected. The DB, RS,
   and R/W pins have internal pullups, so open collector drivers may be
   used with them.
   
   Power consumption: Modules use between 10 and 25mW (2 to 5 mA), not
   counting the backlight, roughly proportional to number of rows and
   columns.
   
   Be careful when hooking power to the module. Reversing +5V and GND
   will destroy the unit. (Personal experience, eh.) Carefully examine
   your datasheet to correctly identify Pin 1.
   
   2.2 Character set None of the standard ASCII control codes
   [chr(1)-chr(31), chr(127)] are implemented.
   
   Standard ASCII is used for chr(32) through chr(125) '}' <00100000b,
   01111101b>
   
   The lower case characters do not have decenders. This is because some
   LCD's (those with 5x7 dots or 5x8 dots) would chop off the bottom.
   Lower case characters with decenders appear near the top of the
   character table. You can access them readily by adding 128 <10000000b>
   if you want decenders and have a 5x11 dot unit that will properly
   display them.
   
   Eight user-defined characters are displayed by chr(0) through chr(7),
   and redundantly with chr(8) through chr(15). <00000000b, 00000111b,
   00001000b, 00001111b>
   
   chr(16) to chr(31) are undefined. <00010000b, 00011111b>
   
   chr(126) is a right arrow -> <01111110b>
   
   chr(127) is a left arrow <- <01111111b>
   
   chr(128) through chr(159) are undefined. <10000000b, 10011111b>
   
   chr(160) through chr(223) are katakana (Japanese) characters.
   <10100000b, 11011111b>
   
   You might find chr(223) useful, it looks like the degree symbol (it's
   a 3x3 box in the upper lefthand corner), and chr(165) <10100101b>, a
   dot in the center of the character.
   
   chr(224) through chr(255) are Greek and other symbols. <11100000b,
   11111111b>
   

11100000b  LC alpha
11100001b  LC 'a' with two dots over it
11100010b  LC beta
11100011b  LC epsilon
11100100b  LC mu
11100101b  LC sigma
11100110b  LC rho
11100111b  decending LC 'g'
11101000b  radical (square root sign)
11101001b  katakana character
11101010b  decending LC 'j'
11101011b  tiny 3 by 3 'x' in upper left corner
11101100b  cent sign
11101101b  UC 'L' with two horizontal bars (pounds Sterling?)
11101110b  LC 'n' with a bar over it
11101111b  LC 'o' with two dots over it
11110000b  LC 'p' with decender
11110001b  LC 'q' with decender
11110010b  LC theta
11110011b  infinity symbol
11110100b  LC omega
11110101b  LC 'u' with two dots over it
11110110b  UC sigma
11110111b  LC pi
11111000b  LC 'x' with a bar over it
11111001b  decending LC 'y'
11111010b  katakana character
11111011b   "        "
11111100b   "        "
11111101b  division symbol (dash with a dot above and below it)
11111110b  blank
11111111b  solid black cursor

   2.3 Instruction Set
   
   Binary data from bit7 to bit 0. If using a 4-bit interface, bit7-bit4
   of data are sent first, then bit3-bit0, on sucessive enable cycles.
   
   The following instructions are sent with RS (register select) and R/W
   (read/write) both low.
   
   Clear display 00000001
   clears display and returns cursor to home position (address 0)
   
   Home cursor 0000001x
   returns cursor to home position, returns a shifted display to original
   position. Display data ram is unaffected. x=don't care
   
   Entry mode 000001ab
   sets cursor move direction and specifies whether or not to shift
   display a=1: increment, a=0: decrement, b=1: with display shift.
   decrement is for languages that write from right to left.
   
   On/off control 00001abc
   turn display on or off, turn cursor on or off, blink character at
   cursor on or off a=1: display on, b=1: cursor on, c=1: blink character
   at cursor position
   
   Cursor/shift 0001abxx
   move cursor without changing display data ram, shift display without
   changing display data ram a=1: shift display, a=0: move cursor, b=1:
   to the right, b=0: to the left x= don't care
   
   Function set 001abcxx
   set interface data length, mode, font a=1: 8-bit, a=0: 4-bit, b=1:
   1/16 duty, b=0: 1/8 or 1/11 duty, c=1: 5x10 dots, c=0: 5x7 dots
   
   Character ram address set 01aaaaaa
   aaaaaa=lower 6 bits of ram address to point to, i.e. to read or write
   custom characters. MSB's are always 01, so character generator ram
   resides from 64 (40h) to 127 (7Fh).
   
   Display ram address set 1aaaaaaa
   aaaaaaa=7 lower bits of ram address to point to, i.e. reposition
   cursor. MSB is always 1, so display ram is from 128 (80h) to 255
   (FFh).
   
   Data write operation:
   
   RS=1, R/W=0, data on bit7 to bit0
   data is written to current cursor position and cursor is incremented
   
   Data read operation:
   
   RS=1, R/W=1, bit7 to bit0 hi-z (inputs to CPU)
   data is read from current cursor position
   
   Read the Busy Flag:
   
   RS=0, R/W=1, bit7 to bit0 hi-z (inputs to CPU)
   bit7=1: busy, bit7=0: OK to send, bit6-bit0 returns current address
   counter.
   
   2.4 Timing
   
   Execution times: Clear display and home cursor 1.64ms, all others
   40us, except read busy flag which is complete in a single enable cycle
   (or two cycles, in 4-bit mode). These execution times mean that after
   an operation, the CPU must do Busy Flag checks until the BF (bit 7) is
   0, or else wait more than the execution time before the next operation
   when the connection to the module from the CPU is write-only.
   
   Enable cycle time (TcycE)
   1000ns min
   Operation cycle time cannot be less than 1 microsecond
   
   Enable pulse width, high (PWEH)
   450ns min
   Enable pulse must be at least 450 nanoseconds long, no maximum length
   
   Enable rise and decay time
   25ns max
   Enable line must change state (L->H or H->L) in less than 25ns
   
   Address setup time (tAS)
   140ns min
   Register Select and R/W lines must be valid 140ns before enable pulse
   arrives
   
   Address hold time (tAH)
   10ns min
   RS and R/W must be valid at least 10 ns after enable goes low
   
   Data delay time (tDDR)
   320ns max
   When doing a read, the return data will be valid within 320ns of
   enable going high
   
   Data hold time, read (tDHR) 20ns min
   When doing a read, the return data will be valid at least 20ns after
   enable goes low
   
   Data setup time (tDSW)
   195ns min
   When doing a write, data on lines bit7-bit0 (or bit7-bit4 in 4-bit
   mode) must be valid at least 195 ns before enable goes low
   
   Data hold time, write (tH)
   10ns min
   When doing a write, data on lines must be valid for at least 10ns
   after enable goes low
   
   Generally, there are no max time requirements on the user except
   Enable rise time. An LCD module can be driven with just toggle
   switches for data, RS, and R/W, and a debounced pushbutton on the
   enable line.
   
   WRITE:
   

    ___ _____________________________ ___________
RS  ___X_________valid_RS_level______X__________
       |                             |
       |                             |
       |<--tAS-->|        tAH-->|    |<--
    ___|         |              |    |____________
R/W ___\_________|___R/W_low____|____/_____________
                 |              |
                 |<----PWEH---->|
                 |              |
                 |<-------------|-------TcycE----->|
                 |______________|                  |_________
E   _____________/              \__________________/
                                |
                     |<--tDSW-->|
                     |       -->|    |<--tH
    _________________|_______________|________________
dat _________________X__valid_data___X____________

   READ:
   

    ___ _____________________________ ___________
RS  ___X_________valid_RS_level______X__________
       |                             |
       |                             |
       |<--tAS-->|        tAH-->|    |<--
    ___|_________|__   _    ____|____|____________
R/W ___/         |  R/W high    |    \_____________
                 |              |
                 |<----PWEH---->|
                 |              |
                 |<-------------|-------TcycE----->|
                 |______________|                  |_________
E   _____________/              \__________________/
                 |              |
          tDDr-->|   |<--       |
                     |       -->|    |<--tDHR
    _________________|_______________|________________
dat _________________X__valid_data___X____________

   2.5 Memory map
   
   2.5.1 Custom characters:
   
   I haven't figured out yet how to write custom characters. Please help!
   Character generator ram appears to reside at 40h to 7Fh in memory.
   There is room for 8 characters of 8 rows each.
   
   2.5.2 Addressing display ram:
   
   16x1 module is arranged as two 8-character lines side by side.
   
   "Line 1" addresses are 80h to 87h
   "Line 2" addresses are C0h to C7h
   
   So, as you write characters to the module, the cursor will
   automatically increment until you get to the 9th character--you have
   to move the cursor to address C0h before writing the 9th character on
   the 1x16 module.
   
   16x2 module is two lines by 16 chars
   Line 1 addresses are 80h to 8Fh
   Line 2 addresses are C0h to CFh
   
   20x1 module
   Line 1 addresses are 80h to 93h
   
   20x2 module
   Line 1 addresses are 80h to 93h
   Line 2 addresses are C0h to D3h
   
   20x4 module
   Line 1 addresses are 80h to 93h
   Line 2 addresses are C0h to D3h
   Line 3 addresses are 94h to A7h
   Line 4 addresses are D4h to E7h
   
   40x2 module
   Line 1 addresses are 80h to A7h
   Line 2 addresses are C0h to E7h
   
   2.6 Initialization
   
   Modules with Hitachi controllers will properly self-initialize if Vcc
   rises from 0 to 4.5v in a period between .1mS and 10mS. I suppose an
   RC circuit would be needed to keep powerup rise time as slow as .1ms,
   so the manual initialization will be required in most applications. If
   you do use auto initialization, it will come up in this mode: 8-bit
   interface, 1/8 duty cycle (1 line mode), 5x7 font, cursor increment
   right, no shift. On most displays, you want to switch to 1/16 duty
   cycle (2 line mode) because for all but the 20x1, there are two
   logical lines as the controller sees it. If you have an 8x11 dot
   matrix module, you'll want to switch to the 5x10 font as well (the
   11th line is the cursor).
   
   2.6.1 Initialization for 8-bit operation:
  
1) POWER ON

2) Wait 15ms

3)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0   0   0   0   1   1   x   x   x   x

x=don't care

4) Wait 4.1ms

5)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0   0   0   0   1   1   x   x   x   x

6) Wait 100us

7)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0   0   0   0   1   1   x   x   x   x

8) Wait 4.1ms

9)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0   0   0   0   1   1   1   F   x   x

8-bit operation
1/16 duty cycle
F=font, 1 for 5x11 dot matrix
        0 for 5x8 dot matrix

10) Wait 40us

11)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0   0   0   0   0   0   1   0   0   0

Display off, cursor off, blink off

12) Wait 40us

13)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0   0   0   0   0   0   0   0   0   1

Clear screen, cursor home

14) Wait 1.64ms

15)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0   0   0   0   0   0   0   1   1   0

Increment cursor to the right when writing,
don't shift screen

15 and a half!! (addendum)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0   0   0   0   0   0   0   1   1   0    Increment cursor to the right
                                         when writing, don't shift screen
Wait 40us


RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0   0   0   0   0   0   1   1   C   B    Turn on display,
					 C=1: turn cursor on, B=1: make 
					 character at cursor position blink
(end addendum)

16) Wait 40us

17) INITIALIZATION COMPLETE

   2.6.2 Initialization for 4-bit operation:
   
   First four instructions are nybbles, then the following are bytes,
   sent on consecutive enable cycles (no delay necessary between
   nybbles), most significant first, followed by least significant
   nybble.
   

1) POWER ON

2) Wait 15ms

3)
RS R/W DB7 DB6 DB5 DB4
0   0   0   0   1   1

4) Wait 4.1ms

5)
RS R/W DB7 DB6 DB5 DB4
0   0   0   0   1   1

6) Wait 100us

7)
RS R/W DB7 DB6 DB5 DB4
0   0   0   0   1   1

8) Wait 4.1ms

9)
RS R/W DB7 DB6 DB5 DB4
0   0   0   0   1   0

4-bit operation

10) Wait 40us

11)
RS R/W DB7 DB6 DB5 DB4
0   0   0   0   1   0

12)
RS R/W DB7 DB6 DB5 DB4
0   0   1   F   x   x

4-bit operation
1/16 duty cycle
F=font, 1 for 5x11 dot matrix
        0 for 5x8 dot matrix
x=don't care

13) Wait 40us

14)
RS R/W DB7 DB6 DB5 DB4
0   0   0   0   0   0

15)
RS R/W DB7 DB6 DB5 DB4
0   0   1   0   0   0

Display off, cursor off, blink off

16) Wait 40us

17)
RS R/W DB7 DB6 DB5 DB4
0   0   0   0   0   0

18)
RS R/W DB7 DB6 DB5 DB4
0   0   0   0   0   1

Clear screen, cursor home

19) Wait 1.64ms

20)
RS R/W DB7 DB6 DB5 DB4
0   0   0   0   0   0

21)
RS R/W DB7 DB6 DB5 DB4
0   0   0   1   1   0

Increment cursor to the right
when writing, don't shift screen

21 and a half!!!  (addendum)
>RS R/W DB7 DB6 DB5 DB4 
>0   0   0   0   0   0   
>0   0   0   1   1   0    Increment cursor to the right
>                         when writing, don't shift screen
> 
>Wait 40us

RS R/W DB7 DB6 DB5 DB4
0   0   0   0   0   0
0   0   1   1   C   B    Turn on display, C=1: turn cursor on,
			 B=1: make character at cursor position blink
(end addendum)

22) Wait 40us

23) INITIALIZATION COMPLETE

   3.0 Interfacing
   
   3.1 Manual test circuit
   
   

                                             __________
                                            |          |
                            GND---*---------| 1        |
                                  <         |          |
                             10K   ><--.    |          |
                                  <    |    |          |
                            +5V---*---------| 2        |
                                       |    |          |
                                        `---| 3        |
               RS                           |          |
        ,-----switch------------------------| 4        |

        |                                   |          |
        |      +5V-----.           GND------| 5        |
        |              |                    |          |
        |              # 3.3k pullup resis. |          |
        |   Enable     |  |\                |          |
        *--pushbutton--*--|  >o-------------| 6        |
        |              |  |/ 74LS04 inverter|          |
        |             ---                   |          |
        |             --- 1uF cap           |          |
        |              |                    |          |
        |    DB0       GND                  |          |
        *---switch--------------------------| 7        |
        |                                   |          |
        |    DB1                            |          |
        *---switch--------------------------| 8        |
        |                                   |          |
       ~~~                                 ~~~        ~~~
       ~~~                                 ~~~        ~~~
        |    DB7                            |          |
        *---switch--------------------------| 14       |
        |                                   |__________|
        |
        GND

   3.2 Interfacing to a CPU bus
   
   These modules use an interface like those in Motorola and Zilog
   systems. R/W on the module can come from the R/W line on the CPU,
   which is set up about the same time as the address, while RS can be
   selected by the low order address line A0. Select Enable by ANDing the
   output from your address decoding and the E clock. Address decoding
   can be done with a magnitude comparator like the 74LS688, or if you
   have address space to spare, with just the high order address line
   (hogging a big chunk of addressing space).
   
   Because Intel CPUs use separate read and write lines, and they are not
   set up ahead of time, R/W as well as RS must be set via address lines.
   Then the Enable signal may be generated from (NOT(/RD AND /WR)) AND
   PSEN).
   
   Using the data bus method limits CPU clock speed because of the tDDR
   read delay and the TcycE and PWEH requirements of the Hitachi
   controller.
   
   3.3 Interfacing to a CPU port
   
   Another interface is the use of 7 I/O bits from a port. In this case,
   driving the module is very simple in 4-bit mode. Example:
   

      |     .--------
      |     |
  PA0 |-----| DB0
  PA1 |-----| DB1
  PA2 |-----| DB2
  PA3 |-----| DB3
  PA4 |-----| R/W
  PA5 |-----| RS
  PA6 |-----| E
  PA7 |--   |
      |     `--------

   First, put the most significant nybble on PA3-PA0, and the appropriate
   R/W and RS signals on PA5 and PA4, and PA6 low. Then toggle PA6 high.
   Then toggle PA6 low. Then put the least significant nybble on PA3-PA0,
   then toggle PA6 high, toggle PA6 low. 40 microseconds later, you can
   send the next character. There's no need to worry about cycle timings
   at all with any but the most blinding speed CPUs. Just be sure to
   notice that toggling PA6 is done by itself, while the other pins are
   held constant.
   
   If you have port pins to spare, then an 8-bit interface can be done
   with 11 port pins (10 for write only).
   
   If you don't expect to ever be reading back from the LCD, you can
   conserve resources by grounding R/W, saving a pin, and thus using
   digital outputs instead of bidirectional ports.
   
   Sample in-line assembly code, by Jordan Nicol, for implementation
   under Dunfield's Micro-C for the Miniboard can be found on ftp
   cher.media.mit.edu It uses port pins PA7-PA3 for 4-bit data and PC6
   and 7 for RS and E.
   
   3.4 Interfacing to the Parallax BASIC STAMP
   
   Sample program with physical hookup described in commented code can be
   found on the ftp site wpi.wpi.edu in the /stamp directory. It's a CPU
   port hookup as described above. The application also involves use of a
   radio control servo.
   
   3.5 Serial interface
   
   A way to save even more I/O space is to use a serial interface,
   requiring just 3 digital output port pins. It uses a shift register
   with serial-in, parallel-out, and output latch.
   

               ________________         __________
_____         |  74LS595       |       |          |
     |        |              QA|-------|DB4       |
     |--------|>ser. clock   QB|-------|DB5       |
CPU  |        |              QC|-------|DB6       |
OUT  |--------|>latch        QD|-------|DB7       |
PORT |        |              QE|-------|RS        |
     |--------|serial data   QF|-------|E         |
_____|        |              QG|--     |          |
       10Kohm |              QH|--     |          |
       pullup |                |       |          |
   +5V--^^^---|\Reset          |   .---|R/W       |
        .-----|\OE             |   |   |__________|
        |     |________________|   GND
        GND

   This method (which could be adapted to turn any 8-bit digital output
   into up to 64 8-bit digital outputs, albeit at a slow speed) uses just
   three pins. It does take more processor time to implement, but it is
   "care free" because it will take more than 40us for most controllers
   to send a byte this way, so a whole screen rewrite could be done
   without worrying about timing.
   
   The Amateur Robotics column in June '94 Nuts & Volts demonstrated how
   to use this technique with the 68hc11's SPI port, using MOSI, SCK, and
   /SS. This would be especially handy with a non-networked Miniboard,
   which has MOSI, MISO, SCK, and /SS conveniently routed to the top left
   corner where resistor pack 2 goes. The experimenter could put the
   contrast potentiometer and latch on a daughterboard mounted underneath
   the LCD module.
   
   The End of part I by Chris Burian.
   
   HTML butchering by Filip Gieszczykiewicz <filip@alpha.med.pitt.edu>

--------------------------------------------------------------------------
Part 2 of 3

                  A Technical Paper on the Technology

   Fundamental Liquid Crystal Display Technology: an introduction for the
   basic understanding of LCDs
   
   Version: 1.00
   Date : August 18, 1993
   
   Copyright 1992-93 by Scott M. Bruck
   
   Copyright Notice: This document is copyright by Scott M. Bruck. It may
   be distributed freely electronically in its complete form including
   references and copyright notices. This document may not be included in
   any publication without written permission from the author.
   
   Please address any questions or comments to the EMAIL address listed
   below:
   
   Written By Scott M. Bruck <sbruck@em.drl.mei.co.jp>
   Matsushita Electric Industrial Co., Ltd.
   Liquid Crystal Display Development Center
   Development Group #1
   Moriguchi-Shi, Osaka 570 JAPAN
   
   In no way does this document represent the views or policies of
   Matsushita Electric Industrial Co., Ltd.
   
   Every effort was made to insure the validity of this document.
   
   
     _________________________________________________________________
   
   Introduction:
   
   Since the introduction, rapid decline in price, and increased
   availability of notebook computers capable of operating Graphical User
   Interfaces (GUIs--MacOS and Windows), there has been an increased
   interest in flat panel display technology. A notebook/palmtop computer
   requires a light weight, durable, and reliable display. Liquid Crystal
   Display technology has met these requirements and as a result,
   virtually all notebook computers are equipped with some form of LCD.
   This FAQ is intended to address the general confusion concerning LCDs
   that has arisen recently by explaining the technology, operation, and
   characteristics of this important display device.
   
                  LIQUID CRYSTAL DISPLAY FUNDAMENTALS:
                                       
    1. A general discussion of how liquid crystal displays work.
    2. A basic introduction to the chemistry, structure, and properties
       of liquid crystals used in displays.
    3. An overview of display structure, assembly, and related technology
       is summarized.
       
        ADDRESSING TECHNOLOGY: PASSIVE AND ACTIVE MATRIX DISPLAYS:
                                       
    4. The differences between Active and Passive matrix display
       addressing techniques is examined
    5. Color technology applicable to liquid crystal displays is
       discussed.
       
               NEW TECHNOLOGY AND QUESTIONS ANSWERED:
                                       
    6. State of the art displays being prototyped are described.
    7. A list of TFT display manufacturers is summarized and a list of
       what notebook computers use what TFT display.
    8. Solutions to questions proposed on Internet news groups not
       covered in the body of the LCD FAQ text.
       
              LCD FAQ 1.0: LIQUID CRYSTAL DISPLAY FUNDAMENTALS
                                       
   1.0 General Characteristics and LCD Modes
   
   Liquid Crystal Displays (LCDs) are categorized as nonemissive display
   devices, in that respect, they do not produce any form of light like a
   Cathode Ray Tube (CRT). LCDs either pass or block light that is
   reflected from an external light source or provided by a back/side
   lighting system. There are two modes of operation for LCDs during the
   absence of an electric field (applied Power); a mode describes the
   transmittance state of the liquid crystal elements. Normal White mode:
   the display is white or clear and allows light to pass through and
   Normal Black Mode: the display is dark and all light is diffused.
   Virtually all displays in production for PC/Workstation use are normal
   white mode to optimize contrast and speed.
   
   1.1 LCD Cell Switching and Fundamentals
   
   A simplified description of how a dot matrix LCD display works is as
   follows: A twisted nematic (TN) LC display consists of two polarizers,
   two pieces of glass, some form of switching element or electrode to
   define pixels, and driver Integrated Circuits (ICs) to address the
   rows and columns of pixels. To define a pixel (or subpixel element for
   a color display), a rectangle is constructed out of Indium Tin Oxide
   -- a semi-transparent metal oxide (ITO) and charge is applied to this
   area in order to change the orientation of the LC material ( change
   from a white pixel to a dark pixel). The method utilized to form a
   pixel in passive and active matrix displays differs and will be
   described in later sections. Figure 1 illustrates a cross sectional
   view of a simple TN LC display. Figure 2 depicts a dot matrix display
   as viewed without its metal module/case exposing the IC drivers.
   
   Looking directly at the display the gate or row drivers are located
   either on the left or the right side of the display while the data or
   column drivers are located on the top (and or bottom) of the display.
   New thin display module technology mounts the ICs on conductive tape
   that allows them to be folded behind the display further reducing the
   size of the finished module. An IC will address a number of rows or
   columns, not just 1 as pictured in figure 2.
   
   Figure 1: Cross Section of a Simple LC Display
   

        viewer
/////////////////////////////////////  Polarizer
_____________________________________  glass
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~  Liquid Crystal
_____________________________________  glass
\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\  Polarizer
        backlight

   Figure 2: LCD panel and IC driver locations
   

________________________________________
|                                       |
|                       IC      IC      | Source/Column ICs
|                       |               |
|                       |               |
|IC---------------------Pixel           |
|                                       |
|IC <---- Gate Line/Row IC              |
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

   * An IC driver will address a number of row/column lines and not just
   the single pixel in the diagram above
   
   Polarizers are an integral part of a LCD display, possessing the
   unique property of only passing light if it is oriented in a specific
   (oriented) direction. To utilize this phenomena in TN LC displays, the
   bottom polarizer orients incoming light in one direction. The oriented
   light passes through the LC material and is either unaltered or "bent"
   90 degrees. Depending on the orientation of the top polarizer, this
   light will either pass through or be diffused. If the light is
   diffused, it will appear as a dark area. Figure 3 is a simple
   illustration of the sequence of events that occur when light passes
   through a simple twisted nematic LC display.
   
   Figure 3: Polarized Light and its use in a TN LC display
   

Light (unoriented) will be defined as:   !#$%&|-
Polarizer Orientation is defined by:    ( $ or # )
($ polarizer will only pass $ light)
(# polarizer will only pass # light) THEREFORE:

Light    Polarizer   result   LC (90   result  Polarizer   Image
Input    type        passed   degree   passed  type        output
                              twist)
                
!##$%%&|-> |  #  | -> #### -> ~~~~~ -> $$$$ ->| # | ------> Black

!##$%%&|-> |  #  | -> #### -> ~~~~~ -> $$$$ ->| $ | ------> White

   1.2 Liquid Crystal Material
   
   1.21 Fundamentals
   
   Please note, I am not a chemist, so I will keep this section as simple
   and concise as possible. Liquid crystals encompass a broad group of
   materials that posses the properties of both a solid and a liquid.
   More specifically, they are a liquid with molecules oriented in one
   common direction (having a long range and repeating pattern--
   definition of a crystal), but have no long range order in the other
   two directions. For example, in figure 4 all the lines are oriented in
   the Y direction (up and down), but they posses no common ordering in
   the x direction (disorder is assumed in the Z direction). To more
   easily visualize this, think of figure 4 as one thin slice (one layer
   of molecules to be exact) of a block of material. If you examined
   another slice, the molecules would still be oriented in the Y
   direction, but they would be in different positions along the X-axis.
   By stacking millions of these thin slices, the Z direction is built up
   and as a result of the change in relative position on the x-axis, the
   Z direction has no long range order.
   

^ Y
|                 Figure 4
|
|
|
|    ||||    |||     ||      |       |||||
|
|        ||||||||     |||||||||||||     ||||    |
|
|    ||||||       |||||        ||||    ||||
|  |||||||
|
|------------------------------------------------------> X

   * The Z direction is coming out of the page toward the reader
   
   The liquid crystals used for display technology are thermotropic
   liquid crystals; they exhibit desired characteristics over a specific
   temperature range. This is the primary reason why LCDs do not operate
   properly when they are too cold or too warm. If liquid crystals are
   too cold, they will not twist and the display will not form an image.
   If the display is too warm, the resistance of the liquid crystal
   material changes and this alters the properties of the display and
   performance suffers. Liquid crystal material for display use is
   normally referred to as TN (STN, DSTN, MSTN, and etc.) or Twisted
   Nematic--sometimes known as TNFE or Twisted Nematic Field Effect. It
   is called TWISTED since the crystals are twisted 90 degrees (or more
   for STN) from the top piece of glass to the bottom piece of glass. (TN
   usually refers only to a 90 degree twist.) Field Effect (a direct
   correlation is the semiconductor MOSFET), refers to the LC material's
   ability to align parallel or perpendicular to an applied electric
   field. As a result, using twisted or untwisted liquid crystal and two
   polarizers; an applied electric field can force the LC material into a
   particular alignment effectively diffusing or passing light through
   the top polarizer.
   
   As a note of interest, polarizers are also one of the major reasons
   that LC displays require bright back lighting. The polarizers and
   liquid crystal materials absorb more than 50% of the incident light.
   As a result, even though the actual display is a very low power
   device, the power hungry back lighting makes a LCD module one of the
   primary causes of short battery life in notebook computers. Due to the
   fact that the LC material has optical properties and effectively bends
   light, the problem of viewing angle effects occur. When the user is
   not directly in front of the display the image can disappear or seem
   to invert (dark images become light and light images become dark).
   However, LC material and polarizer technology is rapidly improving and
   that improvement is showing up in brighter displays with greater
   viewing angles.
   
   1.22 Liquid Crystal Alignment
   
   Liquid crystals must be aligned to the top and bottom pieces of glass
   in order to obtain the desired twist. In other words, the 90 degree
   twist is formed by anchoring the liquid crystal on one glass plate and
   forcing it to twist across the cell gap (the distance between the two
   glass plates) when contacting the second plate. Furthermore, The
   actual image quality of the display will be dependent on the surface
   alignment of the LC material. The method currently used for aligning
   liquid crystals was developed by the Dai-Nippon Screening (English=
   Big Japan Screening) Company. The process consists of coating the top
   and bottom sheets of glass with a Polyimide based film. The top piece
   of glass is coated and rubbed in a particular orientation; the bottom
   panel/polyimide is rubbed perpendicular (90 degrees for TN displays)
   with respect to the top panel. It was discovered that by rubbing the
   polyimide with a cloth, nanometer (1 X 10 - 9 meters) size grooves are
   formed and the liquid crystals align with the direction of the
   grooves. It is common that when assembling a TN LC cell, it will be
   necessary to eliminate patches of nonuniform areas. The two parameters
   required to eliminate the nonuniformities and complete the TN LC
   display are pretilt angle and cholesteric impurities. TN LC cells
   commonly have two problems that affect uniformity following assembly:
   reverse tilt and reverse twist. Reverse tilt is a function of the
   applied electrical field and reverse twist is common when no
   electrical field is applied. Reverse twist is eliminated by the
   introduction of cholesteric additives and reverse tilt is eliminated
   by introducing a pre-tilt angle to the LC material. The pre-tilt angle
   also determines what direction the LC molecules will rotate when an
   electrical field is applied. Pre-tilt angle can be visualized by
   considering the normal position of the LC molecule to be flat against
   the glass plate, by anchoring one edge and forcing the other upward by
   a specific number of degrees, a pretilt angle is established.
   
   1.23 Liquid Crystal Display Names and classes
   
   Before discussing the different types of LC displays the topic of
   Birefringence must be explained. When a light ray strikes a crystal (
   or crystal-like material), it will be split into two separate light
   beams; with one beam perpendicular (offset by 90 degrees) from the
   other. Since the beams travel different paths, they reach the viewer's
   eyes at slightly different times. This is an essential point, it may
   cause the color or polarity of the display to change when viewed at
   angles where the viewer may see both rays.
   
   For active matrix displays, in order to maximize contrast and gray
   scale reproducibility, Twisted Nematic (TN) is utilized. This material
   is twisted 90 degrees from the top to bottom glass panels. STN or
   Super Twisted Nematic is chemically distinct from TN and the twist
   angle is usually greater than 200 degrees. Furthermore, due to the
   large twist angle, the actual alignment of the polarizers for STN LCDs
   are not perpendicular, but adjusted to find the best direction
   (rotation) for optimum display characteristics. The STN material is
   rotated in a way so the change from transmission to dispersion is very
   abrupt and therefore can respond quickly to small changes in voltage.
   Figure 5 illustrates the response characteristics of a TN curve and
   Figure 6 shows the response characteristics of a STN curve which will
   further clarify these points.
   

100%    |                       Figure 5
        |       Typical Response of a Normal White TN Display
T       |
R       |************
A       |             *
N       |               *
S       |<-- Zone I->     *
M       |                   *
I       |                     *
T       |                       *
T       |                         *
A       |                           *
N       |             <----Zone II--- * --------->
C       |                               *
E       |                                  *       <--Zone III-->
        |                                     *
        |                                       *
        |                                          *************
0%      |________________________________________________________>
                     Vt (Threshold Voltage)
        Applied Voltage

   1.24 The TN Liquid Crystal Response Curve
   
   The most prominent feature of the TN response curve is the central
   linear region between the two flat areas (Zone II). Zone I describes
   the white color of the display when no electric field is applied. In
   other words, the display will transmit virtually all the introduced
   light. On the other hand, in Zone III, the display will diffuse light
   and appear dark. The middle region can display gray scale or an image
   somewhere between White and Black. The key point here is that you must
   be able to very carefully control the voltage applied to the LC cell
   and maintain it for one duty cycle (before that pixel is addressed
   again) in order to produce accurate colors. For this reason, this type
   of LC material is primarily used for active matrix LCDs.
   
   COMMONLY ASKED QUESTION NOTE: because the LC material is partially
   twisted in the gray scale area, when looking at a display at an off
   angle the colors tend to shift and sometimes invert due to
   birefringence.
   
   COMPUTER APPLICATION NOTE: The TN response curve does not have to be
   utilized for gray scale, in order to make a simpler display, improve
   viewing angle, and use cheaper IC drivers; the Apple Powerbook 170's
   TFTs (thin film transistors) drive the TN response curve directly into
   region 3. This gives all the speed/contrast advantages of a TFT
   display and cheaper manufacturing cost, but provides no gray scale.
   
   1.25 The STN Liquid Crystal Response Curve
   
   The Key to understanding the STN curve is simply that due to the
   addressing method applied, only a small amount of voltage is available
   to change the LC material from transmittance to a dispersion state.
   For this reason, the shape of the curve has nearly a 90 degree shift
   between Zone I and Zone II regions; in other words, it goes ballistic
   and nearly straight up ! This property allows the LC material to shift
   from white to black at its threshold voltage (VT) without being
   concerned with partial transmission (gray scale). Furthermore, the 90
   Degree curve shape means that gray scale is not available from the LC
   material itself and the driving circuits must provide the necessary
   fixes for levels of gray.
   
   STN displays inherently have a yellow on blue appearance (anyone
   remember the old Zenith Laptops ?). Because many individuals found the
   yellow and blue appearance undesirable, a number of techniques were
   developed to convert the STN image to a black on white scheme. DSTN,
   developed by Sharp Corporation, was the first commercial black and
   white conversion of the STN display and refers to Double Super Twisted
   Nematic. DSTN displays are actually two distinct STN filled glass
   cells glued together. The first is a LCD display as described
   previously, the second is a glass cell without electrodes or
   polarizers filled with LC material for use as a compensator which
   increases contrast and gives the black on white appearance. The
   drawbacks are a heavier module, a more expensive manufacturing
   process, and a more powerful backlighting system.
   
   FCSTN is Film Compensated STN and is now the most commonly used STN
   display technology on the market. FSTN, monochrome STN, and Polymer
   film STN are all standard STN displays with a polymer film applied to
   the glass as a compensation layer instead of the second cell as in the
   case of the DSTN. This simpler and more importantly cost effective
   method provides the preferred black on white image for this display
   technology. However, once again, this design lowers the transmittance
   of light and requires a more powerful back lighting system.
   
   COMMONLY ASKED QUESTION NOTE: Why are STN displays slow ? Due to the
   method used to address passive matrix (STN/DSTN) displays and the high
   density of pixels required for standard VGA displays, the liquid
   crystal material must respond to an extremely small change in voltage.
   In developing these materials for this voltage characteristic, there
   was a reduction in the switching speed. A slow display can best be
   illustrated by the tendency of the cursor to "submerge" or disappear
   when rapidly moved across the screen. Another common example is the
   blurring of images when they quickly move across the display as in the
   case of high speed games. A fast display is less than 40 milliseconds,
   most STN type displays are between 200 and 250 milliseconds. However,
   some new LC mixtures are reaching 150 millisecond speeds.
   
   COMMONLY ASKED QUESTION NOTE: What is Contrast ? Contrast is defined
   as the ratio of black to white, more simply put, how black is black
   when next to a white or clear pixel. In terms of numbers, passive
   matrix LCDs are usually able to produce a contrast ratio of
   approximately 13 - 20:1; in real terms you get a set of different
   grays and blues but no true blacks.
   

100%    ^
        |                      Figure 6
T       |
R       |    ********
A       |            *
N       |             *
S       |<-Zone I----> *<-----------Zone II--------------------->
M       |              *
I       |              *
T       |              *
T       |              *
A       |             *
N       |            *
C       |           *
E       |          *
        |          *
        |          *
        |          *
        |           *
        |             **************************
0%      ------------------------------------------------------->
                        Vt Threshold Voltage
        Applied Voltage

   1.3 Liquid Crystal Display Assembly
   
   Once the switching devices or electrodes have been fabricated on the
   glass halves and the polyimide film has been applied & rubbed, spacer
   balls (usually 4 to 8 micrometers [1 X 10 - 6 meters] in diameter) are
   sprayed on one half of the display. Spacer balls are used to insure
   that the glass plates remain a certain distance apart over the entire
   area of the display; this is also known as cell gap. If the cell gap
   is not uniform, an image will appear different from one end of the
   display to the other. If the spacer balls are not applied correctly,
   they will collect and the user will be able see them as strange areas
   of non-uniform dust or distortion. (Single spacer balls are too small
   to see and they are not black dots.) If the Display has a very large
   cell gap, when you apply slight pressure to the display by touching it
   with your finger, you will see the image change and the LC material
   shift under the glass. Doing this does not damage the display, but
   take care when bringing any sharp objects, such as pen or pencils,
   near the screen; it is very easy to damage the polymer film and or
   polarizers on the display.
   
   The two glass panels are then aligned and glued together with an
   epoxy. During panel assembly, if dirt is trapped between the two glass
   plates, you most likely will see these as annoying spots on the
   display. During the application of the glue, one corner is left open.
   In a vacuum chamber, the liquid crystal material is drawn into the
   display through the open corner. Upon completion, the remaining hole
   is filled with another epoxy. The LC material will align itself to the
   grooves in the polyimide and spread out around the spacer balls.
   
   After final assembly, excess glass is cut and driver ICs are mounted.
   The finished display is mounted onto a backlight assembly (also known
   as an inverter assembly) and encased in metal. There are a number of
   methods for backlighting a LC display. STN displays usually have a
   side, top, or bottom lighting system. In simple terms, this is where
   the fluorescent tube is mounted. For example, in a side-lit display
   one or two fluorescent tubes will be located at the left and or right
   edges of the display. A fluorescent tube normally 4 mm in diameter is
   used. This is dispersed by a plastic plate around the entire area of
   the display. A dispersion plate looks like a white sheet with small
   holes; each of the holes provides a small point of light. On top of
   the dispersion plate, a diffuser is placed. A diffuser takes the
   numerous points of light and uniformly spreads it out over the entire
   area of the display. The net effect is providing a backlighting source
   around 4 or 5 mm thick !
   
   An Active matrix display, especially color modules, transmit much less
   of the incident light and require more elaborate backlighting systems.
   An active matrix TFT display has a matrix fabricated on one piece of
   glass; the metal lines and transistor elements are not transparent and
   block a significant percentage of light. In order to obtain higher
   contrast, newer displays incorporate what is called a black matrix.
   This is a black film that surrounds the pixel elements (this can be on
   the matrix, but is usually around the color filters); although this
   yields higher contrast, it also reduces brightness. Further
   complicating this, the polarizers and the color filters reduce the
   output to less than 5% of the incident light. As a result, most
   backlighting systems designed for active matrix based displays usually
   consist of 4 or 5 four mm tubes placed directly behind the display
   with a diffuser plate to insure uniform irradiation. Therefore, they
   are called backlit. This method of lighting makes the display slightly
   larger, heavier, and greatly increases power consumption. The final
   metal encased display is called a display module or sub-assembly and
   this is what the end user or notebook manufacturer receives.
   
     ADDRESSING AND COLOR TECHNOLOGY (PASSIVE AND ACTIVE MATRIX DISPLAYS)
                                       
   2.0 General Overview:
   
   Addressing describes the method employed to transfer charge (data or
   the display image) from the outside world to the display. Unlike a
   CRT, which is just a surface of phosphors scanned with a beam of
   electrons in a vacuum, a liquid crystal display is an array of
   conductors with metal (or metal like) lines running in both horizontal
   and vertical directions. For the case of a CRT, the electrons travel
   through a resistance free medium (vacuum) and deliver a clear
   consistent signal. The charge traveling through the metal lines of a
   LCD matrix is affected by the properties of the metal. As a result,
   the magnitude and waveform of the applied charge can vary from one end
   of the display to the other. This variation imposes limitations on
   display quality and capabilities.
   
   2.1 Addressing: Passive and Active Matrix Displays
   
   There are distinct differences between active and passive matrix
   displays, but two factors make the greatest impact on potential
   customers. Active matrix displays can cost twice as much as an
   equivalent passive matrix display and add more than $1000 to the cost
   of a notebook form-factor computer. However, active matrix displays
   produce a stunning and bright image without ghosting or artifacts that
   rivals the quality of CRTs. Furthermore, even with the price
   differential, manufacturers are able to sell every active matrix color
   notebook they can produce.
   
   2.11 Liquid Crystal Cell Charging
   
   In general terms (regardless of display type), in order to protect the
   liquid crystal material from deteriorating, cells are addressed by
   alternating current (AC), not direct current (DC). There is no
   resultant charge in the LC material following two addressing cycles;
   build up of charge in the LC material will permanently damage it. In
   other words, a positive and then an equal but opposite negative charge
   is applied to the LC material every other frame. By applying dual
   polarity addressing, the LC material changes twist direction every
   other cycle and the net charge is zero. Furthermore, since the liquid
   crystal material is changing twist directions every other cycle,
   screen savers or screen inverters are not required and in reality do
   absolutely nothing. Passive matrix displays utilize DIRECT ADDRESSING;
   the charge is applied directly from the drivers to the pixel element.
   Active matrix displays utilize INDIRECT ADDRESSING; the charge is
   "filtered" through a switch before reaching the pixel element.
   
   2.12 Driving Methods: Passive Matrix Displays
   
   Passive matrix displays have rows of electrodes on one half of the
   display glass and columns of electrodes on the other. The electrodes
   are usually fabricated out of Indium Tin Oxide (ITO), which is a
   semi-transparent metal oxide. When the two pieces of glass are
   assembled into a display, the intersection of a row and column form a
   pixel element. Furthermore, if a pulse is sent down one row and a
   specific column is grounded, the established electric field can change
   the state of liquid crystal(from white to black). By repeating this
   process (display scanning) an image can be formed on the display.
   Problems arise as the number of rows and columns increase. With higher
   pixel density, the electrode size must be reduced and the amount of
   voltage necessary to drive the display rapidly increases. Furthermore,
   higher driving voltage creates a secondary problem; charging effects.
   Even though only one row and column are selected, the liquid crystal
   material near the row and column being charged are affected by the
   pulse. The net result is the pixel selected is active (dark), but the
   areas surrounding the addressed point are also partially active
   (grays). The partially active pixels reduce the display contrast and
   degrade image quality. A final problem is the speed of the STN
   material, a display must be able to react in less than 40 milliseconds
   for performance similar to a CRT. Most STN materials are between 150
   and 250 milliseconds and can not switch from black to a white image
   that quickly. This problem results in disappearing cursors and blurred
   images when high speed graphics are utilized
   
   COMMONLY ASKED QUESTION NOTE: What is STN Gray Scale ? As discussed in
   part I section 1.24, the STN curve does not possess an intrinsic gray
   scale capability like the TN curve, therefore driving methods have
   been developed to create the illusion of true gray scale. Gray scale
   can be derived from frame-rate control and dithering/space modulation.
   Frame-rate control quickly switches on and off a pixel, the eye
   perceives this as gray. Dithering or space modulation is accomplished
   by alternately keeping some pixels black and some white in a
   checkerboard layout; when using this method, the layout is in a random
   order. If dithering is in a regular (repeating) pattern, it is
   detectable by the human eye. In real world applications, combinations
   of both technologies are applied to commercial displays. The result,
   however, is sometimes wavy or moving grays. ( The image appears to be
   moving in waves or a solid color appears to be in motion when a large
   area is set to a specific gray level.)
   
   RECENT TECHNOLOGY NOTE: What are Dual Scan STN Displays ? This is
   simply taking currently made color STN displays and applying some
   previously developed technology. Back in the late 1970's and early
   1980's liquid crystal chemistry was not as advanced and in order to
   build high data content displays, manufacturers were forced to build
   two displays on one glass plate. A dual scan display utilizes similar
   technology. Instead of running the columns down the entire display,
   they are terminated in the center of the display, a small gap is left,
   and the line is continued to the bottom of the display. In reality,
   you now have two 640 X 240 displays on one glass plate. Therefore, if
   IC drivers are mounted on the top and the bottom of the display, the
   charge must only travel half the distance of a normal display. As a
   result, the effects of the contrast limitations discussed in section
   2.12 can be reduced. The end result appears to be a brighter display,
   but in reality it is only improved contrast (the blacks appear
   darker). The dual scan STN display still suffers from the ghosting and
   artifact problems inherent in all slow STN displays.
   
   2.13 Driving Methods: Active Matrix Displays
   
   In order to eliminate the problems of the STN/passive matrix display,
   the active matrix display was developed. Active matrix displays have a
   thin film Transistor or diode on the glass substrate that indirectly
   addresses each pixel element. Depending on the display type,
   application, or manufacturer, the TFT may be comprised of amorphous
   silicon (a-Si) or polycrystalline silicon (p-Si), The TFT completely
   isolates one pixel element from the others in the display and
   eliminates the problem of partially active pixels. Simply put, the TFT
   acts as a switch ! When a row of TFTs are addressed the gate lines are
   active-- the switch is turned on, this allows charge to flow from the
   columns into the pixels and set the image for the frame cycle. Once a
   row has been addressed, the gate line is reversed biased (the switch
   is turned off) to insure that no charge can pass from the columns into
   the pixel element. Thus, the pixel is now completely isolated as the
   rest of the display is addressed. The LC material acts as a capacitor
   and stores charge. After a charge is placed on a liquid crystal cell (
   the defined pixel area), it begins draining similar to a discharging
   capacitor (an exponential function). As a result, unless the display
   can be written quickly (all 480 rows scanned and the return to the top
   of the display to rescan starting from row 1 for a VGA display) the
   image will not be uniform from the top to the bottom of the display as
   the LC material starts to untwist. In order to insure charge storage
   for one frame and carefully control charge on a pixel element, TFT
   displays incorporate a second capacitor in parallel with the LC
   material. The combined capacitance gives active matrix displays the
   essential capability to accurately maintain the amount of charge
   applied; thus reliable partial charges can be utilized and gray scale
   or full color displays are possible. With proper drivers and high
   quality TFTs, 256 gray scales have been obtained with quality that
   surpasses that of CRTs. TN material can also switch much faster than
   STN, thus 40 millisecond TFT displays are common yielding CRT like
   speed.
   
   COMMONLY ASKED QUESTION NOTE: What is cross Talk ? Cross talk is best
   described as the effect when a dark image (box or widow shape) is
   placed in the middle of a white background. Faint vertical and
   horizontal lines will be seen from the edge of the window proceeding
   to the edges of the screen. This can be caused by poorly designed
   drivers or poorly made TFTs. The off selected TFTs are not completely
   off and some charge, very strong at the edge of a window, has leaked
   into the pixels creating the effect. This is a common problem and is
   being addressed by the manufacturers of TFT based displays.
   
   2.2 Color Display Pixel Layout and Yields In order to build a fully
   functional color VGA display, a TFT LCD must have 480 X 640 X 3 pixel
   elements. The 640 X 480 is the well understood VGA pixel layout (640 X
   400 for the Apple Powerbook series and 640 X 480 for the 180c), except
   640 red, 640 green, and 640 blue columns or stripes of color pixels
   are now required. This is a total of 921,600 TFTs that must work in
   order to build a perfect display. Using a semiconductor analogy, it is
   similar to building a 1 Megabit DRAM on a 10 inch glass plate; not an
   easy task considering a particle smaller than the diameter of the
   human hair can destroy a single TFT. Achieving a 100 % yield or a
   perfect display is virtually impossible, thus even though manufacturer
   yields are starting to reach 60% (for sellable devices) prices are
   very high. Furthermore, if 4 defective pixels are found on a color VGA
   screen, this already represents a 99.99 % pixel yield-- not bad for
   any process. For the most part, the most common pixel defect is caused
   by some form of contamination damaging a TFT and preventing it from
   turning the pixel off (seen as bright spots on a dark background).
   There are two layouts for pixels on TFT displays. The most common for
   computer applications is the STRIPE layout. A stripe layout has
   repeating stripes of red, green, and blue columns across the display.
   For multimedia and high density arrays (projection LCD modules), a
   triad pixel layout is used. A triad layout has the three color
   sub-pixels in a triangle shape. Figure 7 illustrates the difference
   between the two layouts.
   
   Figure 7: Color Pixel Layouts
   

Stripe Layout                           Triad Layout
-------------------------------------------------------
RGB     RGB     RGB                      R     R     R
RGB     RGB     RGB                     G B   G B   G B

   Note: What is a color filter? A color filter works by absorbing
   specific wavelengths of light and only passing light of a certain
   wavelengths (In other words, a red filter will remove all wavelengths
   of light except for red -- thus it looks red !). White light is made
   up of a spectrum of wavelengths, so it can yield the red, green, and
   blue for displays. However, when filtering out the unwanted
   wavelengths, the overall brightness is reduced.
   
   COMMONLY ASKED QUESTION NOTE: What is a pixel? Unfortunately, in most
   of the literature and magazines, there is not a clear definition as to
   what a pixel is. In its most basic form, a pixel is described as one
   element on a display screen. For a monochrome screen this is an
   adequate description. However a color pixel is actually made up of
   three subpixels: a red, green, and blue pixel. This is sometimes
   called a pixel triad. Therefore care must be taken in describing
   pixels. In terms of this document, a pixel is the entire element
   consisting of red, green, and blue sub subelements. A subpixel
   consists of the individual red, green, or blue elements. Gray scales
   for LC displays are always calculated as a function of subpixels.
   
   2.3 Color Displays: Gray Scales and Bits
   
   Due to the overall poor performance of Passive Matrix color displays,
   only active matrix displays will be specifically discussed. However,
   major points are applicable to both display addressing technologies.
   Unlike an analog CRT, in a digital color TFT active matrix display,
   you literally get what you buy...forever. Even if you upgrade to a new
   video driver or display card, you will still have the same number of
   colors and gray scales. The number of colors is a direct result of the
   number of gray scales a display can reproduce. The standard VGA format
   is rated to display 256 colors, however it can select from a 18 BIT
   CLUT (color look up table) which means the choice of 262,144
   colors(this calculation is based on a bit calculation for a pixel
   triad -- 2 ^ 18 --- see later section on calculations). Intrinsic gray
   scale reproducibility for TFT displays is a result of two factors: the
   quality of the driver ICs used on the display and the resistance of
   the gate metal(the rows of the display). The gate metal must carry a
   clear and undeformed pulse from one end of the display to the other(
   640 X 3 = 19200 lines). If the pulse is not maintained the TN curve
   will not charge to the desired level and the correct color can not be
   displayed. Therefore, the more gray scales required, the greater the
   control that must be exerted over the gate lines. For example, most
   displays sold today can display 256 colors out of 4092 or 512. The 256
   colors is based on the VGA video controller, the 4092 is a display
   limitation. 4092 possible colors indicates that a display can
   reproduce 16 gray scales. This is derived from 16 (red) X 16 (blue) X
   16 (green) = 4092 possible colors. Once again, dithering can be used
   to extend this, but there are displays in limited production that can
   reproduce 256 gray scales or more than 16 million colors ! Most
   current TFT color displays feature 3 bit drivers (where 2 raised to
   the third power yields 8); these drivers can produce a total of 512
   colors. This is more than adequate unless later on you decide you wish
   to pursue some multimedia functions which require more than 32 levels
   of gray scale. Although the controller and the computer may be fast
   enough to handle the functions, 8 or 16 gray scales will be
   inadequate-- your image will not be what you expect (It will look like
   a collection of color shadows). Sharp has recently demonstrated 10
   inch 640 X 480 displays running on Apple Macintoshes displaying 64
   gray scales. These 6 bit drivers are supposedly entering production
   and will enter the commercial market shortly. The color reproduction
   of these displays is excellent.
   
   2.4 Understanding Digital Color Pixels
   
   4 Bits, 8 Bits, 16 Bits, 24 Bits Just how many colors can they
   actually generate ? Digital video divides the number of colors or gray
   scales into a distinct number of points. Based on these "POINTS" the
   system can generate a fixed number of colors or gray scales.
   Manufacturers tend to play games with numbers, so sometimes it is very
   difficult to understand "BIT" color talk. First of all, the bit system
   is based on the binary system so: 1 Bit color, which is 2 raised to
   the first power is 2. In other words a black & white display where the
   pixel has a state of being either on or off. This can currently be
   extended to 24 bits which (at 2 to the 24 power) yields more than 16
   million gray scales. OK, now that we understand how gray scales are
   calculated, lets convert this to a color display: Once again,
   manufacturers play a game with numbers and here we introduce bpp or
   BITS PER PIXEL. Now depending on manufacturer, a pixel can be made up
   of 1 subpixel (the individual Red, Green, and Blue pixels) or can be a
   composite of all three colors. If we examine a 16bpp system the
   following calculations are applicable: 2 raised to the 16th power is:
   65536. So if the system is 16 bpp for the combined primary colors, the
   system can produce a total of 65536 colors. If the system produces 16
   bpp for all three colors then 65536 X 65536 X 65536 = 2.8 X 10^14
   colors. The small table below summarizes the Bits confusion. Triad
   Pixel refers to a combination of the RED/GREEN/BLUE pixels. Subpixel
   refers to the individual red, green, or blue pixel. The number of gray
   scales for a monochrome display is always the same as a triad
   calculation bpp display. The numbers listed down the columns refer to
   how many gray scales or colors that a system configuration can
   produce. CRT based color is usually calculated as the triad pixel
   calculation.
   

Bits/Colors    Mono or Triad Pixel      Subpixel (R/G/B)
--------------------------------------------------------
1                       2               8
4                       16              4096
8                       256             1.68X10^7
16                      65536           2.81X10^14
24                      1.68X10^7       4.72X10^21

   COMMONLY ASKED QUESTION NOTE: What is analog video ? Unlike digital or
   bit based video analog video is based on a continuous flow of data.
   The wave form can be thought of as a continuous wave of points with
   the distance between points so small that it is impossible to
   differentiate between them. In other words, it can theoretically
   provide an infinite number of gray scales. VGA is an analog system and
   VGA CRTs are analog displays. The advantage of an analog display is
   that when you upgrade your video card and drivers to handle more
   colors, your existing monitor should be able to operate with the
   extended color ranges. NEC makes an analog XVGA TFT LCD, but due to
   power handling requirements, it is not suitable for battery based
   portable computers.
   
   COMMONLY ASKED QUESTION NOTE: Why are TFT Color Displays Expensive ?
   There are numerous reasons for this. As discussed above, displays with
   large numbers of defective pixels can not be sold and as a result,
   yield is usually thought to be the major problem. In reality, one
   should be aware that the largest cost of TFT displays are the
   materials utilized for production. Since Japanese manufacturers have
   not standardized the size of displays yet, each manufacturer has
   specific material needs (glass, holders for machines, robots, and
   etc.). This fact alone keeps display prices extremely high since
   material and machine suppliers can not make standard parts for an
   entire industry at this time.
   
   COMMONLY ASKED QUESTION NOTE: How many gray scales are required for
   multimedia operations ? Usually 64 gray scales or more are required
   for true multimedia operations. TFT LCDs with 64 gray scales will
   probably be available in volume within a year.
   
   COMMENT: Why are some color TFT displays much brighter than others ?
   The brightness of a screen is determined by two related factors; the
   size of the screen and the aperture ratio of the pixels. On the
   surface of an active matrix array there are both pixels and
   electronics, as a result of the opaque electronics, some of the area
   that light could pass through is blocked. The ratio of light passing
   through the pixel to the entire area of the pixel and associated
   electronics is called the aperture ratio. The larger the ratio is, the
   more light that can pass through the pixel and the brighter the image
   on the display will be. Furthermore, if the display itself is bigger,
   there is more room for the pixels and the result is more light passing
   through the individual pixels. For this reason, DTIs 10 inch display
   found in the IBM Thinkpad 700c is much brighter than some of the
   smaller 8.4 and 9.5 inch TFT displays.
   
   2.4 Basic Principles of TFT Operation
   
   For all intensive purposes, a TFT can simply be considered a switch;
   when selected (on) it allows charge to flow through it and when off it
   acts as an barrier preventing or at least restricting the flow of
   charge. As mentioned earlier, a TFT is a MOS FET device or a Metal
   Oxide Semiconductor Field Effect Transistor. The gate line can be
   considered the "switch" of the transistor, with this you turn it on,
   partially on, or off. The Source and drain are the entrance and exit,
   respectively, for the charge you want to pass through the switch. In
   the case of a display, this is the charge that you want to appear on
   the pixel. Looking at Figure 7, source and drain metal electrodes are
   separated by an amorphous silicon (a-Si) semiconductor layer; with the
   absence of charge the a-Si layer acts as an insulator or resistor and
   prevents the flow of charge from the source to drain; thus isolating
   the pixel from the rest of the display. SiNx or silicon Nitride is the
   gate insulator and forms the gate dielectric; electrons do not pass
   from the gate line into the transistor, but are used to influence the
   charge distribution in the semiconductor layer. A MOS FET that fits
   this description (you turn it on)is called an enhancement device. When
   a positive charge is placed on the gate line, electrons (or negatively
   charged particles) will begin to collect in the area above the gate,
   on the other side of the Silicon Nitride (SiNx) in the a-Si. When the
   charge on the gate is increased to a certain point, called the VT or
   threshold voltage, enough electrons will have collected in the a-Si to
   change it from an insulator to a conductor. In other words, you build
   up a channel of electrons, so if there are electrons at the source
   (high) and nothing at the drain (low), the electrons will begin to
   move through the electron filled channel until the charge is the same
   at both sides or you turn the transistor off. The result is a charging
   of the pixel and a change in the state of the liquid crystals. The
   unique aspect of this device is the nonlinear characteristics after
   the TFT passes through Vt. It exponentially moves to a conduction
   state (usually 6 to 8 orders of magnitude) and makes it very easy to
   turn a TFT on or off around the Vt value. For more information on MOS
   FET device operation, pick up a book on Semiconductor Physics or Solid
   State Physics. The above is only meant as a basic simplified
   description of MOS device operation.
   
   2.5 TFT Connections
   
   The gate line of the TFT determines whether or not the TFT will pass a
   charge into the pixel. These are controlled by the row bus-lines. On a
   standard VGA display, the gate lines would be the 480 horizontal
   lines. The source lines of the TFT are connected to the column or data
   bus-lines. These lines provide the charge for the pixel or contain the
   data for the image. The drain lines of the TFT are directly attached
   to the ITO pixel, this transfers the charge from the semiconductor
   region into the pixel.
   
   Figure 7: Thin Film Transistor Cross Section
   

^^^^^^^^^^^^^^^^^^^^^^^^        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
        Source Metal    ^       ^       Drain Metal
                        ^       ^
                    $$$$$$$$$$$$$$$$$$
                    $   SiNx         $
        ******************************************
        *               a-Si    Semiconductor    *
*********                                        *************
                ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                ~               SiNx        ~
                ~    __________________     ~
~~~~~~~~~~~~~~~~~   |                  |    ~~~~~~~~~~~~~~~~~~
                    |   gate           |
___________________________________________________________

                        glass

___________________________________________________________

   References:
   
   Solid State Technology, December 1988, page 65 Amorphous Silicon
   Technology, Chapter 3 page 77 High-resolution panels target laptop
   computers, EDN, April 23, 1992 A. Miyaji, M. Yamaguchi, A. Toda, H.
   Mada, and S. Kobayashi, Control and Elimination of Disclinations in
   Twisted Nematic Liquid Crystal Displays, IEEE Trans. E. D. Vol. ED-24,
   No.7, 1977, pg. 811 Kaneko, E., Liquid Crystal TV Displays: Principles
   and Applications of Liquid Crystal Displays, KTK Scientific Publishers
   Flat Panel Display 1993 (Japanese Publication) from Nikkei Electronics
   Proceedings of SID; May 1993 Various articles from SID Information
   Display and Electronic Engineering Times Magazine Acknowledgments:
   
   I would like to thank Mike Schuster (SCHUSTER@PANIX.COM) for
   commenting on clearness and general understanding while compiling this
   FAQ.

-----------------------------------------------------------------------
Part 3 of 3

   Jump to:
   
     * LCD pintout & setup
     * Where to buy LCD displays
     * LCD programming
     * LCD programming sample (6502)
     * Controlling LCD with a Motorola 68hc11
       
   (From Steve Hill)
   
   LCD pintout & setup
   
   An LCD backlight would be run off of 5vDC, while an EL backlight uses
   the inverter that you described. The "two extra" pins are for the
   backlight and are not polarized - hook the outputs of the inverter to
   these pins.
   
   Vss should be hooked to ground - I believe your origional post may
   have been in error.
   
   Vdd should be hooked to +5v.
   
   Vo (pin 3) should be connected to the wiper on a 10K pot which is
   accross pins 1 and 2.
   
   Pin 4 is register select. When high you are writing data (characters
   to the display) and when low you are writing to control registers.
   
   Pin 5 is Read/Write. Can be tied low since a basic implementation has
   no need to read from the display registers - but is useful in more
   advanced applications.
   
   Pin 6 is Enable. The data on pins 7-14 is latched on the falling edge
   of this signal. Just strobe it low after you have set up data on the
   data pins.
   
   Pins 7-14 are data I/O. Using all these pins for an 8 bit interface.
   Use only DB4-7 (pins 11-14) for a 4 bit interface.
   
   Prior to writing characters to the display, it must be initialized. A
   typical initialization sequence is as follows: (assumes R/W tied low)
   
    1. Power ON
    2. Function SET (8 data bits, 2 lines, 5x7 dot format) RS=0 Data=0x38
    3. Function SET (repeat above 4 times) RS=0 Data=0x38
    4. Function SET RS=0 Data=0x38
    5. Function SET RS=0 Data=0x38
    6. Entry Mode (Increment one, no shift) RS=0 Data=0x06
    7. Display ON/OFF (display ON, Cursor ON, Blink OFF) RS=0 Data=0x0E
    8. Display Clear RS=0 Data=0x01
    9. DD RAM Address Set RS=0 Data=0x80
       (note the address could be different for your display - try it -
       consult data sheet) Also note that the second display line
       probably isn't at an address that is consecutive with the first
       (0x80-0x80 typical first line; 0xC0-0xCF typeical second line) Now
       you're ready to write data. Just set RS high and write the
       character codes you want. DDRAM address is automatically
       incremented. To get to the second line you need to set the DDRAM
       address as shown above.
       
       (From Bill Mayhew)
       
       LCD programming
       
       [Most LCDs have same/similar programming]
       

RS R/W B7 B6 B5 B4 B3 B2 B1 B0

0  0   0  0  0  0  0  0  0  1        Clear Display

0  0   0  0  0  0  0  0  1  X        Return Home

0  0   0  0  0  0  0  1  D  S        Entry Mode Set
                                     D: 0=direction -, 1=direction +
                                     S: 0=no shift, 1=shift

0  0   0  0  0  0  1  D  C  B        Display on/off
                                     D: 0=disply off, 1=on
                                     C: 0=cursor off, 1=on
                                     B: 0=blink off, 1=on

0  0   0  0  0  1  S  R  X  X        Display or Cursor Shift
                                     S: 0=cursor only, 1=both
                                     R: 0=right; 1=left

0  0   0  0  1  D  N  F  X  X        Set data interface
                                     D: 0=8 bit, 1=4 bit
                                     N: 0=F works, 1=F is ignored
                                     F: 0=5x7 dots, 1=5x10 dots

0  0   0  1  A  A  A  A  A  A        Set char gen RAM address
                                     Lets you select one of 64
                                     chars for loading a bit map

0  0   1  A  A  A  A  A  A  A        Set display RAM address
                                     Lets you select an address
                                     in the display buffer.  With
                                     this you can write in a pos-
                                     ition that is off the viewable
                                     display.

0  1   B  A  A  A  A  A  A  A        Read busy flag, address pointer
                                     If B=1, display is updating.
                                     Also returns address of last
                                     data transfer.

1  0   D  D  D  D  D  D  D  D        Write Data
                                     Writes to Display if previous
                                     instruction was SET DISPLAY
                                     RAM ADDR.  Writes to char gen if
                                     previous instruction was SET
                                     CHAR GEN RAM ADDR.

1  1   D  D  D  D  D  D  D  D        Read Data
                                     Reads from Display if previous
                                     instruction was SET DISPLAY
                                     RAM ADDR.  Reads from char gen if
                                     previous instruction was SET
                                     CHAR GEN RAM ADDR.
   It is best to read the busy flag to see if the previous operation you
       requested is complete. You can also go by timing if you are trying
       to minimize the number of input operations. Timing:
       

Clear               82uS to 1.64 mS  (assuming 250 KHz clock)
Return home         40uS to 1.6 mS
Entry mode set      40uS
Display on/off      40uS
Display/cursor shf  40uS
Function set        40uS
Set CG RAM addr     40uS
Set disp RAM addr   40uS
Read busy flag       1uS
Write Data          40uS
Read Data           40uS
   
         _____________________________________________________________
       
       (From Bill Mayhew)
       
       LCD programming sample (6502)
       

        .nolist
        .page
        .title  "Watch dog program"
        .list
        .eject
;
;watch dog single board computer system
;Bill Mayhew,  Neoucom, January 1989
;traget cpu Rockwell 6502 with 1 MHz clock
;
;revised March 6, 1989 to support warm boot into
;bypass mode.
;
;6522 chip registers
outb    .equ    $c000
outa    .equ    $c001
ddrb    .equ    $c002
ddra    .equ    $c003
t1l     .equ    $c004
t1h     .equ    $c005
t2l     .equ    $c008
t2h     .equ    $c009
acr     .equ    $c00b
pcr     .equ    $c00c
flags   .equ    $c00d
icr     .equ    $c00e
;
;assorted page zero locations
asave   .equ    $00             ;used by intrpt
ysave   .equ    $01             ;used by intrpt
casave  .equ    $02             ;used by chrout
cysave  .equ    $03             ;used by chrout
caddr   .equ    $04             ;address of cursor on display unit
cmode   .equ    $05             ;current mode of cursor
pasave  .equ    $06             ;used by print
pysave  .equ    $07             ;used by print
msgbase .equ    $08             ;word used to hold beginning of message
slcount .equ    $0a             ;used by sleep routine
sysave  .equ    $0b             ;used by sleep
tmin    .equ    $0c             ;used in count-down timer
min     .equ    $0d
tsec    .equ    $0e
sec     .equ    $0f
tenth   .equ    $10
twait   .equ    $11
owait   .equ    $12
getsw   .equ    $13             ;vector switch for char input
getvec  .equ    $14             ;word vector for char input routine
cookie  .equ    $16             ;word 'magic cookie' to determine reset mode
;
;
        .org    $f000           ;assemble into system ROM
entry   .equ    *
        sei                     ;kill interrupts whilst setting up
        cld                     ;operate in binary mode
        lda     #$07            ;only bits 0, 1 and 2 are outputs
        sta     ddra            ;enable ddra
        lda     #$ff            ;ddr output mask -- all bits on
        sta     ddrb            ;enable ddrb
        lda     #$c2            ;mask to enable timer #1 & ca1 trigger
        sta     icr             ;set interrupt control register
        lda     #$40            ;mask for t1 continuous mode
        sta     acr             ;set auxiliary control register
        lda     #$fb            ;ss relay on, lcd in text mode, beeper off
        sta     outa            ;place bits in output register
        lda     #(50000 % $100) ;loop time of 50.000 mS
        sta     t1l             ;least significant byte of timer
        lda     #(50000 >> 8)
        sta     t1h             ;most significant byte of timer
        lda     #$ae            ;mask to generate PB2 pulse on outb write
        sta     pcr             ;set peripheral control register
        jsr     newline         ;initially clear the display
        lda     cookie          ;check magic cookoie; $1234 means warm boot.
        cmp     #$34            ;cookie lsb
        bne     e1              ;continue if not magic value
        lda     cookie+1
        cmp     #$12            ;cookie msb
        bne     e1
        jmp     bypass          ;go to bypass mode if magic value found
e1      lda     #$34            ;set up magic cookie
        sta     cookie          ;lsb
        lda     #$12
        sta     cookie+1        ;msb
        lda     #(init1 % $100) ;get first initial message
        sta     msgbase
        lda     #(init1 >> 8)
        sta     msgbase+1
        jsr     print           ;send line to display
        lda     #3              ;sleep 3 seconds
        jsr     sleep
        jsr     newline
        lda     #(init2 % $100) ;get second initial message
        sta     msgbase
        lda     #(init2 >> 8)
        sta     msgbase+1
        jsr     print
        lda     #3
        jsr     sleep
        jsr     newline
        lda     #(init3 % $100) ;get third initial message
        sta     msgbase
        lda     #(init3 >> 8)
        sta     msgbase+1
        jsr     print
        lda     #3
        jsr     sleep
        lda     #(i1 % $100)    ;initialize char interrupt vector
        sta     getvec
        lda     #(i1 >> 8)
        sta     getvec+1
        lda     #0
        sta     cookie          ;clear cookie
        sta     cookie+1
        lda     t1h             ;reset timer
        cli                     ;interrupts are ok now
;
;
mlp     .equ    *               ;kernel begins here
        lda     #$7             ;reset count-down clock
        sta     tmin
        lda     #0
        sta     min
        sta     tsec
        sta     sec
        sta     tenth
        lda     twait           ;set oldwait-time = this-wait-time
        sta     owait
        sei                     ;can't interrupt print operations
        jsr     newline         ;clear display
        lda     #(resetm % $100)
        sta     msgbase
        lda     #(resetm >> 8)
        sta     msgbase+1
        jsr     print           ;print static element of time display
ml1     ldy     tmin            ;get tens of minutes left
        lda     #9              ;cursor in column 9
        sei                     ;can't interrupt print operations
        jsr     tput            ;put ascii char on display
        ldy     min
        lda     #10
        jsr     tput
        ldy     tsec
        lda     #12
        jsr     tput
        ldy     sec
        lda     #13
        jsr     tput
        ldy     tenth
        lda     #15
        jsr     tput
        cli                     ;o. k. to interrupt now
                                ;
        lda     #0              ;set accum=0
        ldy     #4              ;see if all 5 time bytes are zero
ml2     ora     tmin,y          ;tmin+4, +3, +2, +1, +0
        dey
        bpl     ml2             ;loop if y >= 0
        ora     #0              ;set flags
        beq     mlre            ;do a reset when 00:00.0
                                ;
        dec     tenth
        bpl     ml3             ;skip other digits if >= 0
        lda     #9
        sta     tenth
        dec     sec
        bpl     ml3
        lda     #9
        sta     sec
        dec     tsec
        bpl     ml3
        lda     #5
        sta     tsec
        dec     min
        bpl     ml3
        lda     #9
        sta     min
        dec     tmin
ml3     lda     twait           ;what is our hash count?
        cmp     owait           ;same as before?
        beq     ml3             ;wait for interrupt to change hash count
        sta     owait           ;twait --> owait
ml4     lda     twait
        cmp     owait
        beq     ml4
        sta     owait
        jmp     ml1             ;repeat process for next 1/10 second
                                ;
mlre    sei                     ;can't interrupt power-cycle
        jsr     newline         ;have to reboot because 70 minutes expired
        lda     #(bootm % $100)
        sta     msgbase
        lda     #(bootm >> 8)
        sta     msgbase+1
        jsr     print
        lda     outa
        and     #$fe            ;set bit 0=0
        sta     outa            ;shut off solid state relay
        lda     #30             ;sleep 30 seconds to allow power-clycle
        jsr     sleep
        lda     outa
        ora     #$01            ;set bit 0=1
        sta     outa
        cli                     ;o. k. to interrupt now
        jmp     mlp             ;re-do this routine forever!
;
;
tput    .equ    *               ;ascii print a decimal number in y, cursor in a
        pha
        lda     outa            ;enter command mode
        and     #$fd            ;bit 0=0
        sta     outa
        pla
        ora     #$80            ;set msb
        jsr     chrout
        lda     outa
        ora     #$02            ;enter text mode
        sta     outa
        tya                     ;get decimal #
        clc
        adc     #48             ;adjust for printable ascii
        sta     outb
        rts
;
;
intrpt  .equ    *
        pha
        lda     flags           ;get interrupt flags from 6522 via chip
        and     #$40            ;see if t1 interrupt has happened
        beq     ijmp            ;else it must have been from the CA-1 pin
        inc     twait           ;change hash variable
        lda     t1l             ;read register to clear the flag bit
        lda     flags           ;see if other interrupt is pending
        and     #$02
        bne     ijmp
        pla
        rti                     ;resume processing
                                ;
ijmp    jmp     (getvec)
                                ;
i1      pla                     ;get rid of pushed accumulator
        lda     outa            ;read outa to clear the CA-1 flag bit
        jsr     newline         ;clear display
        lda     #(portm % $100)
        sta     msgbase
        lda     #(portm >> 8)
        sta     msgbase+1
        jsr     print           ;display busy activity message
        lda     #0
        sta     getsw           ;initially exit at end of this sleep
        lda     #(i2 % $100)    ;re-aim vector
        sta     getvec
        lda     #(i2 >> 8)
        sta     getvec+1
        pla                     ;dispose of interrupt vector and flags
        pla
        pla
i1x     cli                     ;"manually" re-enable interrupting
        lda     #1              ;sleep for one second
        jsr     sleep
        sei                     ;disable interrupts for checking vector
        lda     getsw           ;any more sleep?
        bne     i1y
        dec     getsw           ;less sleep now
        jmp     i1x             ;go sleep
i1y     lda     #(i1 % $100)    ;re-aim vector
        sta     getvec
        lda     #(i1 >> 8)
        sta     getvec+1
        cli                     ;o. k. for interrupts now
        jmp     mlp             ;jump back into main loop
                                ;
i2      lda     #1              ;force one more second of sleep
        sta     getsw
        lda     outa            ;read port to reset interrupt
        pla
        rti
;
;
delay   .equ    *               ;wait a short time
        pha
        lda     acr             ;get timer control
        and     #$df            ;mask t2 control bit
        sta     acr             ;update status
        pla
        pha
        sta     t2l             ;load timer latch
        sty     t2h             ;writing MSB triggers timer
wait    lda     flags           ;get flags
        and     #$20            ;mask out the t2 status bit
        beq     wait            ;loop until it times out
        pla
        rts
;
;
sleep   .equ    *               ;sleep for n seconds, n passed in accum.
        sty     sysave
        ora     #0              ;set flags
sl1     beq     slend
        sec
        sbc     #1              ;decrement sleep time
        pha
        lda     #20             ;sleep in 20 50-mS increments
        sta     slcount
sl2     dec     slcount
        bne     sl3
        pla
        jmp     sl1
sl3     lda     #(50000 % $100) ;50 mS time constant
        ldy     #(50000 >> 8)
        jsr     delay
        jmp     sl2
        ldy     sysave
slend   rts
;
;
chrout  .equ    *               ;send char in accum to display
        sta     outb            ;put in PIA output
        sta     casave          ;in case caller wants it back
        sty     cysave
        lda     #120            ;wait 120 uS
        ldy     #0
        jsr     delay           ;burn up some time
        ldy     cysave
        lda     casave
        rts
;
;
putc    .equ    *               ;put char into display, maybe with scroll
        pha
        lda     caddr           ;where is cursor now?
        cmp     #16             ;past last column?
        bne     pc1             ;if not, don't worry, be happy
        lda     cmode           ;check if scrolling is on
        bne     pc2             ;skip this if it is already on
        lda     outa
        and     #$fd            ;bit 1=0, puts lcd in command mode
        sta     outa
        lda     #$07            ;display board code that enables scrolling
        jsr     chrout          ;send
        lda     outa
        ora     #$02            ;bit 1=1, puts lcd in character mode
        sta     outa
        inc     cmode           ;flag the status byte
pc1     inc     caddr           ;show that cursor moved
pc2     pla
        jsr     chrout          ;send user's character
        rts                     ;that's it!
;
;
newline .equ    *               ;clear display & home cursor with full reset
        pha
        lda     outa            ;get status
        and     #$fd            ;bit 1=0, enter command mode
        sta     outa
        lda     #$01            ;display board reset code
        jsr     chrout          ;send to display
        lda     #(5000 % $100)  ;time constant for 5 mS delay
        ldy     #(5000 >> 8)
        jsr     delay           ;burn up some time
        lda     #$34            ;select 5 * 10 bit character set
        jsr     chrout
        lda     #$0c            ;unblank display
        jsr     chrout
        lda     #$06            ;disable display scrolling
        jsr     chrout
        lda     #0
        sta     cmode           ;indicate scrolling is disabled
        sta     caddr           ;cursor is in column zero
        lda     outa
        ora     #$02            ;bit 1=1, enter lcd text mode
        sta     outa
        pla
        rts
;
;
print   .equ    *               ;print a message on entry, msgbase points to ms
g
        sta     pasave
        sty     pysave
        ldy     #0
pl      lda     (msgbase),y     ;get character
        beq     pend            ;if a \0, that's end of msg.
        jsr     putc
        iny
        bne     pl              ;branch always
pend    ldy     pysave
        lda     pasave
        rts
;
;
bypass  .equ    *               ;bypass mode
        lda     #0              ;clear magic cookie
        sta     cookie
        sta     cookie+1
        lda     #(bpassm % $100)
        sta     msgbase
        lda     #(bpassm >> 8)
        sta     msgbase+1
        jsr     print
b1      lda     outa            ;get output port
        ora     #$04            ;turn on beeper
        sta     outa
        lda     #(50000 % $100 )
        ldy     #(50000 >> 8)   ;50 mS time constant
        jsr     delay
        jsr     delay
        jsr     delay
        jsr     delay           ;wait total 200 mS
        lda     outa
        and     #$fb            ;turn off beeper
        sta     outa
        lda     #120            ;sleep for two minutes
        jsr     sleep
        jmp     b1              ;do forever until reset
;
;
init1   .text   "  Watch Cat 1.0"
        .byte   0
init2   .text   "   Bill Ma"
        .byte   %11111001       ;y with lower case descender
        .text   "hew"
        .byte   0
init3   .text   "  NEOUCOM  1989"
        .byte   0
resetm  .text   "Reset in   :  ."
        .byte   0
portm   .text   "   Port Active"
        .byte   0
bootm   .text   "RESETTING SYSTEM"
        .byte   0
bpassm  .text   "  BYPASS MODE"
        .byte   0
;
;
        .org    $f7fa           ;hardwire vectors
        .word   entry           ;NMI points to system entry point
        .word   entry           ;address of system entry point
        .word   intrpt          ;address of IRQ service routine
        .end
   (From Marc Christensen)
       
       Where to buy LCD displays
       
       If you can use 1x16 they are easy to find on the surplus market.
       Timeline 1-800-223-9977 has lots of LCD displays. For example,
       1x16's got for $6.00 - $8.00 with the controllers built into them
       and backlight. They also have a 4 Col x 2 Row for $5.00. Many of
       the displays can use larger characters and fewer lines if you want
       to try that.
       
       Marlin P Jones has a 1x24 without the controller for $1.00.
       
       (From Alan Kilian)
       
       Controlling LCD with a Motorola 68hc11

*
*       Author: Alan Kilian   kilian(at)cray.com
*
*       Title : HC11 LCD driver routines
*
*       File Name : lcd.asm
*
*       Description : This program demonstrates the use of a HC11 processor
*                     to control a LCD panel
*
*       History : 02/10/93 Created.
*                 02/11/93 Added power-up delay
*                 03/17/94 Tried to get reliable operation with 256 X 64 bit
*                          display. Epson LM213B
*                 03/18/94 Added the LCD_RST line to control the *RESET line
*                 03/19/94 Added proper *RESET timeing. Combined SELECT_REG
*                          and STORE_REG into one routine.
*                 03/30/94 Changed to using BSET/BCLR
*                 04/04/94 Finally got BSET/BCLR to work!!!
*
*       Port usage:
*       PORTC Bit0 = DB0 through BIT7 = DB7
*       PORTA Bit7 = E
*             Bit6 = RS
*             Bit5 = RW
*             Bit4 = Reset
*
*       Note : This program is written for the MC68HC811E2 processor running
*              in single-chip mode. It is designed for use with a processor
*              running with an 8 mHz crystal. If you are using a different
*              crystal frequency you will need to re-compute all of the
*              timing values in this code.
*
*              The structure, serial I/O and command processor portions of
*              this program evolved from the program HEXLOB40 written by
*              Fred Martin and Randy Sargent and we thank them greatly.
****************************************************************************

* One-Byte Registers
PORTA   EQU     $1000
PACTL   EQU     $1026
PORTB   EQU     $1004   ; PORT B data register
PORTC   EQU     $1003
DDRC    EQU     $1007
SPCR    EQU     $1028
BAUD    EQU     $102B   ; SCI Baud Rate Control Register
SCCR1   EQU     $102C   ; SCI Control Register 1
SCCR2   EQU     $102D   ; SCI Control Register 2
SCSR    EQU     $102E   ; SCI Status Register
SCDR    EQU     $102F   ; SCI Data Register
* Masks for serial port
PORTD_WOM       EQU     $20
BAUD1200        EQU     $B3
BAUD9600        EQU     $B0
TRENA           EQU     $0C     ; Transmit, Receive ENAble
RDRF            EQU     $20     ; Receive Data Register Full
TDRE            EQU     $80     ; Transmit Data Register Empty

* Masks for the PORTA LCD control signals
LCD_E           EQU     $80     ; Bit 7 of PORTA is an active HIGH "E"
LCD_RS          EQU     $40     ; Bit 6 of PORTA is an active HIGH reg#1
LCD_RW          EQU     $20     ; Bit 5 of PORTA is an active LOW write
LCD_RST         EQU     $10     ; Bit 4 of PORTA is an active LOW reset

* Masks for PORTC direction
ALL_OUTPUT      EQU     $FF     ; 1 = output, 0 = input

* The BUSY bit on PORTC
BUSY            EQU     $80     ; Bit 7 of PORTC

* The names of the LCD registers
MODE            EQU     $00
PITCH           EQU     $01
NCHARS          EQU     $02
DUTY            EQU     $03
CURPOS          EQU     $04
DUMMY1          EQU     $05     ; There is no command 5
DUMMY2          EQU     $06     ; There is no command 6
DUMMY3          EQU     $07     ; There is no command 7
DSLOW           EQU     $08
DSHIGH          EQU     $09
CURLOW          EQU     $0A
CURHIGH         EQU     $0B
WRDAT           EQU     $0C
RDDAT           EQU     $0D
CLRBIT          EQU     $0E
SETBIT          EQU     $0F

* Values for various LCD things
DISPLAY_WIDTH   EQU     256     ; Pixels wide
DISPLAY_HEIGHT  EQU     64      ; Pixels tall
DUTY_CYCLE      EQU     64      ; 1/64 DECIMAL duty cycle
CHAR_WIDTH      EQU     8       ; How wide is the char cell?
CHAR_HEIGHT     EQU     8       ; How tall is the char cell?
CURSOR_LINE     EQU     8       ; Cursor is on line 8 of the char cell

* Bits for the mode command
DISPLAY_ON      EQU     $20     ; Is the display on?
MASTER          EQU     $10     ; Master/Slave mode
BLINK           EQU     $08     ; Does the cursor blink?
CURSOR_ON       EQU     $04     ; Is the cursor displayed?
GRAPHICS_MODE   EQU     $02     ; Graphics or character mode?
EXTERNAL_CG     EQU     $01     ; Is the character generator internal?

*******************************************************************************
*
* zero page RAM definitions. Do not use FCB here. It will stomp EEBOOT20.
*******************************************************************************
*

        ORG     $00             ; The beginning of RAM

**********************************************************************
*                              MAIN CODE                             *
**********************************************************************

        ORG     $F800           ; $F800 is the beginning of EEPROM
*                               ; on a MC68HC811E2 processor

Start:
        LDS     #$00FF          ; Set stack at the top of ram

        LDAA    #ALL_OUTPUT
        STAA    DDRC            ; Set PORTD for all outputs.

        JSR     SERIAL_SETUP

        JSR     LCD_RESET
        JSR     LCD_SET
        JSR     LCD_HOME
        JSR     LCD_HOME

        JSR     PRT_STR

mainloop
        BRA     mainloop

SERIAL_SETUP
        LDX     #$1000
        BCLR    SPCR,X PORTD_WOM        ; turn off wired-or mode
        LDAA    #BAUD9600
        STAA    BAUD
        LDAA    #TRENA
        STAA    SCCR2
        RTS

LCD_RESET
        LDAA    #00
        STAA    PORTA                   ; Reset the LCD panel
        JSR     BIGDELAY
        LDAA    #LCD_RST
        STAA    PORTA                   ; Release the reset line
        JSR     BIGDELAY
        RTS

BIGDELAY
        LDAA    #$FF            ; Delay to allow the LCD panel to power-up
BIG1    LDAB    #$FF
BIG2    DECB
        BNE     BIG2
        DECA
        BNE     BIG1
        RTS

LCD_HOME
        LDAA    #DSLOW          ; Set display address low
        LDAB    #$00            ; Start displaying at address zero
        JSR     SELECT_REG

        LDAA    #DSHIGH         ; Set display address high
        LDAB    #$00            ; Start displaying at address zero
        JSR     SELECT_REG

        LDAA    #CURLOW         ; Set cursor address low
        LDAB    #$00            ; Put the cursor at address zero
        JSR     SELECT_REG

        LDAA    #CURHIGH        ; Set cursor address high
        LDAB    #$00            ; Put the cursor at address zero
        JSR     SELECT_REG
        RTS

PRT_STR LDX     #STR
        LDAA    #WRDAT
PRT0    LDAB    0,X
        CMPB    #'='            ;String terminates with a '=' character
        BEQ     PRT1
        JSR     SELECT_REG
        INX
        BRA     PRT0
PRT1    RTS

PRT_CHR PSHA
        PSHB
        TAB
        LDAA    #WRDAT
        JSR     SELECT_REG
        PULB
        PULA
        RTS

LCD_SET
        LDAA    #$80
        STAA    PACTL

        LDAA    #MODE           ; Command 0 Mode control
        LDAB    #DISPLAY_ON|MASTER|BLINK|CURSOR_ON
        JSR     SELECT_REG

        LDAA    #PITCH          ; Command 1 Character pitch
        LDAB    #CHAR_HEIGHT-1
        ASLB
        ASLB
        ASLB
        ASLB
        ORB     #CHAR_WIDTH-1
        JSR     SELECT_REG

        LDAA    #NCHARS         ; Command 2 Number of characters
        LDAB    #DISPLAY_WIDTH/CHAR_WIDTH
        SUBB    #1
        JSR     SELECT_REG

        LDAA    #DUTY           ; Command 3 Duty cycle
        LDAB    #DUTY_CYCLE-1
        JSR     SELECT_REG

        LDAA    #CURPOS         ; Command 4 Cursor position
        LDAB    #CURSOR_LINE-1
        JSR     SELECT_REG
        RTS


SELECT_REG
        PSHX
        PSHB
        LDX     #$1000
        JSR     WAIT_BUSY
        STAA    PORTC           ; Set the data lines
        BSET    PORTA,X #LCD_RS         ; Set RS high and RW low
        BSET    PORTA,X #LCD_E   ; Set RS and E high
        BCLR    PORTA,X #LCD_E            ; Set RS low also.
        BCLR    PORTA,X #LCD_RS         ; Set E low

        PULB
        STAB    PORTC                   ; Set the data lines
        BSET    PORTA,X #LCD_E          ; Set E High
        BCLR    PORTA,X #LCD_E
        PULX
        RTS

WAIT_BUSY
        PSHB
        BCLR    DDRC,X #BUSY

        BSET    PORTA,X #LCD_RS|LCD_RW
        BSET    PORTA,X #LCD_RS|LCD_RW|LCD_E

WAIT    BRSET   PORTC,X #BUSY *         ; Wait until the BUSY bit goes zero

        BCLR    PORTA,X #LCD_E
        BCLR    PORTA,X #LCD_RW
        BCLR    PORTA,X #LCD_RS

        BSET    DDRC,X #BUSY
        PULB
        RTS

STR     FCC     'Shutter Speed.1 = '

BadInt  RTI                     ; Set all unused vectors here
        Org     $FFC0           ; Where the interrupt vectors are

        FDB     BadInt  * $FFC0 ; Reserved
        FDB     BadInt  * $FFC2 ; Reserved
        FDB     BadInt  * $FFC4 ; Reserved
        FDB     BadInt  * $FFC6 ; Reserved
        FDB     BadInt  * $FFC8 ; Reserved
        FDB     BadInt  * $FFCA ; Reserved
        FDB     BadInt  * $FFCC ; Reserved
        FDB     BadInt  * $FFCE ; Reserved
        FDB     BadInt  * $FFD0 ; Reserved
        FDB     BadInt  * $FFD2 ; Reserved
        FDB     BadInt  * $FFD4 ; Reserved

        FDB     BadInt  * $FFD6 ; SCI Serial System
        FDB     BadInt  * $FFD8 ; SPI Serial Transfer Complete
        FDB     BadInt  * $FFDA ; Pulse Accumulator Input Edge
        FDB     BadInt  * $FFDC ; Pulse Accumulator Overflow
        FDB     BadInt  * $FFDE ; Timer Overflow
        FDB     BadInt  * $FFE0 ; In Capture 4/Output Compare 5 (TI4O5)
        FDB     BadInt  * $FFE2 ; Timer Output Compare 4 (TOC4)
        FDB     BadInt  * $FFE4 ; Timer Output Compare 3 (TOC3)
        FDB     BadInt  * $FFE6 ; Timer Output Compare 2 (TOC2)
        FDB     BadInt  * $FFE8 ; Timer Output Compare 1 (TOC1)
        FDB     BadInt  * $FFEA ; Timer Input Capture 3 (TIC3)
        FDB     BadInt  * $FFEC ; Timer Input Capture 2 (TIC2)
        FDB     BadInt  * $FFEE ; Timer Input Capture 1 (TIC1)
        FDB     BadInt  * $FFF0 ; Real Time Interrupt (RTI)
        FDB     BadInt  * $FFF2 ; External Pin or Parallel I/O (IRQ)
        FDB     BadInt  * $FFF4 ; Pseudo Non-Maskable Interrupt (XIRQ)
        FDB     BadInt  * $FFF6 ; Software Interrupt (SWI)
        FDB     BadInt  * $FFF8 ; Illegal Opcode Trap ()
        FDB     BadInt  * $FFFA ; COP Failure (Reset) ()
        FDB     BadInt  * $FFFC ; COP Clock Monitor Fail (Reset) ()
        FDB     Start   * $FFFE ; /RESET
        END

--------------------End of Entire FAQ and Doc Re: LCD's-------------------


